i2c.map.qmsg

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Fri Apr 04 20:19:27 2008 " "Info: Processing started: Fri Apr 04 20:19:27 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c -c i2c" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "MyDD/i2c.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 61 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_clk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_clk " "Info: Found entity 1: i2c_clk" {  } { { "MyDD/i2c_clk.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_clk.v" 50 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_rreg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_rreg.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_rreg " "Info: Found entity 1: i2c_rreg" {  } { { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_st " "Info: Found entity 1: i2c_st" {  } { { "MyDD/i2c_st.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_st.v" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "i2c_tbuf.v(76) " "Warning (10273): Verilog HDL warning at i2c_tbuf.v(76): extended using \"x\" or \"z\"" {  } { { "MyDD/i2c_tbuf.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_tbuf.v" 76 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_tbuf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_tbuf.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_tbuf " "Info: Found entity 1: i2c_tbuf" {  } { { "MyDD/i2c_tbuf.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_tbuf.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_wreg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_wreg.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_wreg " "Info: Found entity 1: i2c_wreg" {  } { { "MyDD/i2c_wreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_wreg.v" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "i2c " "Info: Elaborating entity \"i2c\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_wreg i2c_wreg:U1 " "Info: Elaborating entity \"i2c_wreg\" for hierarchy \"i2c_wreg:U1\"" {  } { { "MyDD/i2c.v" "U1" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 154 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c_rreg i2c_rreg:U2 " "Info: Elaborating entity \"i2c_rreg\" for hierarchy \"i2c_rreg:U2\"" {  } { { "MyDD/i2c.v" "U2" { Text "E:/Study FPGA/I2C/MyDD/i2c.v" 163 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i2c_act i2c_rreg.v(86) " "Warning (10235): Verilog HDL Always Construct warning at i2c_rreg.v(86): variable \"i2c_act\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 86 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "i2c_act i2c_rreg.v(87) " "Warning (10235): Verilog HDL Always Construct warning at i2c_rreg.v(87): variable \"i2c_act\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "MyDD/i2c_rreg.v" "" { Text "E:/Study FPGA/I2C/MyDD/i2c_rreg.v" 87 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0 "" 0}