ctrl_reg.v

根据外部控制指令和送入的波形参数

// register desciption:
//reg[0]:clk_div_1;   //FPGA 25mHZ 2分频；
//reg[1]:clk_div2;    //CLK_MOD 4MHZ，六分频；
//reg[2]:REF_MEM_CTR, //reference memmory control reg;
//|15---|14---|13---|12---|11---|10---|9----|8----|7----|6----|5----|4----|3----|2-----|1------|0----|
//|no use     |exp_5|exp_4|exp_3|exp_2|exp_1|exp_0|core |size_|size_|size_|size_|ref_  |ref_mem|ref  |
//                                                  |reset| 3   | 2   | 1   | 0   |mem_we|_mode  |     |
//reg[3]:size_num_4k;
//reg[4]:size_num_8k;
//reg[5]:core_state;    //seem to be  no use;
//reg    work_mode;     //直通还是脉压方式的选择；
//reg ref;//参考数据输入方式；
//reg prf_en;  //prf信号使能；测试时用；
//reg core_enable;  //核使能；
//reg frame_prf_num; //高低PRF重频导致的帧组数不同；500->10， 950->18；

module ctrl_reg(
                     CLK,            //dsp clk;33M
                     CLK_FPGA,
                     RESET,          
                     ref_mem_mode,
//                     ref_mem_we,
                     ref_size,
		             ref,
                     FKL_Hprf,  //no use;
                     PRF_500_976,
                     YT_NT,     //test mode use instead  PRF_500_976 面板上测试用的；
                     PRF_SEL,
                     work_mode,
                     frame_prf_num
                     //--------------- ---可能要加些核的状态信息-----------；                         
                     );
 
input                CLK;
input                CLK_FPGA;
input                RESET;
output               ref_mem_mode;
//output               ref_mem_we;   //？？？？？？
output[3:0]          ref_size;
input                FKL_Hprf;
input                PRF_500_976;
input                YT_NT;
output               PRF_SEL;
//output               core_enable;
output               work_mode; 
output[4:0]          frame_prf_num;
output               ref;

//reg [15:0]       REF_MEM_CTR;
//reg [15:0]       core_state;
reg              PRF_SEL;    //0:500 1:950;
reg              ref;
//-------test mode--------//
reg              work_mode;   //0:normal 1:test--bypass;
reg              prf_en;        
reg[4:0]         frame_prf_num;  
//reg              core_enable;
reg[3:0]         ref_size;      
reg              ref_mem_mode;       
      
always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
     ref_mem_mode<=1'b0;
   else
     ref_mem_mode<=1'b1;   //config ref mem mode ref_mem_data;

always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
     ref<=1'b1;
   else
     ref<=1'b0;   //ref frame disable;

/*     
always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
     prf_en<=1'b0;
   else
     prf_en<=1'b1;   //prf signal enable;     
*/

always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
      PRF_SEL  <= 1'b0;
   else
      PRF_SEL  <=1'b0;//PRF_500_976 || YT_NT;       //PRF_500_976==0，ensure core work;8K 

always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
      ref_size<=4'hd;
   else
      if(PRF_SEL==1'b0)
         ref_size<=4'hd;      //4K
      else
         ref_size<=4'hc;      //8k

always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
      work_mode<=1'b0;
   else
      work_mode<=1'b1;    //0:normal  1:bypass;
      
always@(posedge CLK_FPGA or negedge RESET)
   if(!RESET)
       frame_prf_num<=5'h0;
   else  
       if(PRF_SEL==1'b1)
          frame_prf_num<=5'h12;   //18;
       else
          frame_prf_num<=5'ha;   //10;  
        
 endmodule