代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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www.eeworm.com/read/169299/9868208
vhw testwave.vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Thu Apr 06 17:11:47 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9868214
vhw countt1.vhw
-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 14:49:45 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Wa
www.eeworm.com/read/169299/9868309
vhw selwave.vhw
-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 16:03:09 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Wa
www.eeworm.com/read/169299/9868383
vhw d524wave.vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Apr 07 10:07:45 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9868718
vhw d24wave.vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 12 15:09:04 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9868863
vhw dq24wave.vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Wed Apr 12 14:53:31 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9868989
vhw decodewave.vhw
-- D:\FPGA\TEST\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Fri Apr 07 09:31:34 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Ben
www.eeworm.com/read/169299/9869045
vhw mdtest.vhw
-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 15:07:50 2006
--
-- Notes:
-- 1) This testbench has been automatically generated from
-- your Test Bench Wa
www.eeworm.com/read/361963/10026382
c dev_c7200_iofpga.c
/*
* Cisco router simulation platform.
* Copyright (c) 2005,2006 Christophe Fillot (cf@utc.fr)
*
* Cisco 7200 I/O FPGA:
* - Simulates a NMC93C46 Serial EEPROM as CPU and Midplane EEPROM.
* -
www.eeworm.com/read/164962/10080320
txt mealy1.txt
-- Mealy State Machine with Registered Outputs
-- dowload from: www.fpga.com.cn & www.pld.com.cn
library ieee;
use ieee.std_logic_1164.all;
entity mealy1 is port(
clk, rst: in