mdtest.vhw

xilinx xc9572 cpld 实现的伺服电机控制器

-- D:\FPGA\XC_9572
-- VHDL Test Bench created by
-- HDL Bencher 6.1i
-- Tue Apr 25 15:07:50 2006
-- 
-- Notes:
-- 1) This testbench has been automatically generated from
--   your Test Bench Waveform
-- 2) To use this as a user modifiable testbench do the following:
--   - Save it as a file with a .vhd extension (i.e. File->Save As...)
--   - Add it to your project as a testbench source (i.e. Project->Add Source...)
-- 

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY mdtest IS
END mdtest;

ARCHITECTURE testbench_arch OF mdtest IS
-- If you get a compiler error on the following line,
-- from the menu do Options->Configuration select VHDL 87
FILE RESULTS: TEXT OPEN WRITE_MODE IS "results.txt";
	COMPONENT mdecode
		PORT (
			MA0 : In  std_logic;
			MB0 : In  std_logic;
			MC0 : In  std_logic;
			MA1 : In  std_logic;
			MB1 : In  std_logic;
			MC1 : In  std_logic;
			CLR0 : In  std_logic;
			CLR1 : In  std_logic;
			RD : In  std_logic;
			O : Out  std_logic_vector (7 DOWNTO 0)
		);
	END COMPONENT;

	SIGNAL MA0 : std_logic;
	SIGNAL MB0 : std_logic;
	SIGNAL MC0 : std_logic;
	SIGNAL MA1 : std_logic;
	SIGNAL MB1 : std_logic;
	SIGNAL MC1 : std_logic;
	SIGNAL CLR0 : std_logic;
	SIGNAL CLR1 : std_logic;
	SIGNAL RD : std_logic;
	SIGNAL O : std_logic_vector (7 DOWNTO 0);

BEGIN
	UUT : mdecode
	PORT MAP (
		MA0 => MA0,
		MB0 => MB0,
		MC0 => MC0,
		MA1 => MA1,
		MB1 => MB1,
		MC1 => MC1,
		CLR0 => CLR0,
		CLR1 => CLR1,
		RD => RD,
		O => O
	);

	PROCESS
		VARIABLE TX_OUT : LINE;
		VARIABLE TX_ERROR : INTEGER := 0;

		PROCEDURE CHECK_O(
			next_O : std_logic_vector (7 DOWNTO 0);
			TX_TIME : INTEGER
		) IS
			VARIABLE TX_STR : String(1 to 4096);
			VARIABLE TX_LOC : LINE;
		BEGIN
			-- If compiler error ("/=" is ambiguous) occurs in the next line of code
			-- change compiler settings to use explicit declarations only
			IF (O /= next_O) THEN 
				STD.TEXTIO.write(TX_LOC,string'("Error at time="));
				STD.TEXTIO.write(TX_LOC, TX_TIME);
				STD.TEXTIO.write(TX_LOC,string'("ns O="));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, O);
				STD.TEXTIO.write(TX_LOC, string'(", Expected = "));
				IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, next_O);
				STD.TEXTIO.write(TX_LOC, string'(" "));
				TX_STR(TX_LOC.all'range) := TX_LOC.all;
				STD.TEXTIO.writeline(results, TX_LOC);
				STD.TEXTIO.Deallocate(TX_LOC);
				ASSERT (FALSE) REPORT TX_STR SEVERITY ERROR;
				TX_ERROR := TX_ERROR + 1;
			END IF;
		END;

		BEGIN
		-- --------------------
		MA0 <= transport '1';
		MB0 <= transport '0';
		MC0 <= transport '0';
		MA1 <= transport '0';
		MB1 <= transport '0';
		MC1 <= transport '0';
		CLR0 <= transport '1';
		CLR1 <= transport '1';
		RD <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=20 ns
		MA0 <= transport '1';
		MA1 <= transport '0';
		CLR1 <= transport '1';
		RD <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=40 ns
		MC0 <= transport '0';
		MA1 <= transport '0';
		MC1 <= transport '0';
		CLR0 <= transport '0';
		CLR1 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=60 ns
		MC0 <= transport '1';
		MC1 <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=80 ns
		MA0 <= transport '0';
		MC0 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=100 ns
		MC0 <= transport '1';
		MC1 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=120 ns
		MC0 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=140 ns
		MC1 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=160 ns
		MC0 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=180 ns
		MC0 <= transport '1';
		MC1 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=200 ns
		MA0 <= transport '1';
		MC0 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=220 ns
		MB0 <= transport '1';
		MC0 <= transport '1';
		MC1 <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=240 ns
		MC0 <= transport '0';
		MC1 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=260 ns
		MC0 <= transport '1';
		MA1 <= transport '0';
		MC1 <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=280 ns
		MA0 <= transport '0';
		MC0 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=300 ns
		MC0 <= transport '1';
		MC1 <= transport '0';
		-- --------------------
		WAIT FOR 20 ns; -- Time=320 ns
		MC0 <= transport '0';
		MC1 <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=340 ns
		MC0 <= transport '1';
		-- --------------------
		WAIT FOR 20 ns; -- Time=360 ns
		MC0 <= transport '0';
		MC1 <= transport '0';
		-- --------------------
		WAIT FOR 30 ns; -- Time=390 ns
		-- --------------------

		IF (TX_ERROR = 0) THEN 
			STD.TEXTIO.write(TX_OUT,string'("No errors or warnings"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Simulation successful (not a failure).  No problems detected. "
				SEVERITY FAILURE;
		ELSE
			STD.TEXTIO.write(TX_OUT, TX_ERROR);
			STD.TEXTIO.write(TX_OUT, string'(
				" errors found in simulation"));
			STD.TEXTIO.writeline(results, TX_OUT);
			ASSERT (FALSE) REPORT
				"Errors found during simulation"
				SEVERITY FAILURE;
		END IF;
	END PROCESS;
END testbench_arch;

CONFIGURATION mdecode_cfg OF mdtest IS
	FOR testbench_arch
	END FOR;
END mdecode_cfg;