代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
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nh 基于fpga与pc机的地震动信号采集与处理系统的研究与实现（机械电子工程）.nh
www.eeworm.com/read/18472/790359
doc 介绍用fpga设计实现mil-std1553b部接口中的曼彻斯特码编解码器.doc
www.eeworm.com/read/291453/8417570
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/290412/8484286
c jtag.c
// JTAG parallel cable demo code
// (c) fpga4fun.com KNJN LLC 2006
// This code assumes that you have a JTAG parallel cable connected to your PC
// Works with Xilinx parallel III or Altera ByteBl
www.eeworm.com/read/433021/8552038
vhd 简单的锁存器.vhd
-- Latch Inference
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
ENTITY latchinf IS
PORT
(
enable, data : IN BIT;
q : OUT BIT
);
END l
www.eeworm.com/read/387421/8685017
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/282829/9056983
v generic_dpram.v
//synopsys translate_off
`include "timescale.v"
//synopsys translate_on
`define VENDOR_FPGA
//`define VENDOR_XILINX
//`define VENDOR_ALTERA
module generic_dpram(
// Generic synchronous d
www.eeworm.com/read/184532/9095562
mac changefreq.mac
INCLUDE regClock.inc
INCLUDE regBase.inc
; cpld register address define
FPGA_REGS_BASE_PHYSICAL EQU (0x08000000)
JSSR_OFFSET EQU (0x20)
;---------------------------------------
www.eeworm.com/read/167697/9955521
vhd 条件赋值：使用列举类型.vhd
-- Selected Signal Assignment with Enumeration Type
-- Download from: http://www.fpga.com.cn
Library IEEE ;
use IEEE.std_logic_1164.all ;
PACKAGE meals_pkg IS
TYPE MEAL IS (BREAKFAST, LU