代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/17919/767012
txt fpgacom.txt
0
推荐
FPGA板上实现串口通信
FPGA开发板上写的Verilog代码：
功能是从电脑端发送一个字节，然后把它接收回来。
`timescale 1ns / 10ps
`define Tgate 1
module uart_loop (osc,rst_,rxd,sdo,data_ready,framing_error,parity_error);
inpu
www.eeworm.com/read/177512/5324031
ref vhdllib.ref
Div_fre5 NULL E:/secret_document/秘密文档/综合/GMSK/用FPGA实现的gmsk的调制程序/div_fre.vhd sub00/vhpl00
Div_fre5 Behavioral E:/secret_document/秘密文档/综合/GMSK/用FPGA实现的gmsk的调制程序/div_fre.vhd sub00/vhpl01
Difr NULL E
www.eeworm.com/read/177512/5324032
ref hdpdeps.ref
V1 19
AR work/SR3PR_AH/BEHAVIORAL \
FL E:/secret_document/秘密文档/综合/GMSK/用FPGA实现的gmsk的调制程序/sr3pr.vhd \
EN work/SR3PR_AH
FL E:/secret_document/秘密文档/综合/GMSK/用FPGA实现的gmsk的调制程序/gmod.vhd 2004
www.eeworm.com/read/368407/9697057
txt fpgacom.txt
0
推荐
FPGA板上实现串口通信
FPGA开发板上写的Verilog代码：
功能是从电脑端发送一个字节，然后把它接收回来。
`timescale 1ns / 10ps
`define Tgate 1
module uart_loop (osc,rst_,rxd,sdo,data_ready,framing_error,parity_error);
inpu
www.eeworm.com/read/169299/9868238
cdf untitled.cdf
JedecChain;
FileRevision(JESDxxA);
/* NoviceMode */
/* Active Mode BS */
/* Mode BS */
/* Cable ParallelIII lpt1 200000 */
P ActionCode(Cfg)
Device
PartName(xc9572)
File("D:\FPGA\xc_
www.eeworm.com/read/164962/10080349
txt cpu_3rd_package.txt
-- Third Party Package containing functions for Bit_Vector operations
-- download from: www.fpga.com.cn & www.pld.com.cn
-- Cypress Semiconductor WARP 2.0
--
-- Copyright Cypress Semicondu
www.eeworm.com/read/164962/10080375
txt chess_clock.txt
-- Chess Clock
-- some expressions can not be synthetized,only for Simulation. (such as "AFTER 500 ms")
-- download from: www.fpga.com.cn & www.pld.com.cn
PACKAGE chesspack IS
SUBTYPE hour
www.eeworm.com/read/439407/6932045
txt readme.txt
README file: XAPP204 VHDL Reference Design
==========================================
Date: Wed. September 28, 1999
Updates: 12/10/99 - JLB - Compilation with FPGA Express 3.3 and Alliance 2.1i S