fpgacom.txt

FPGA编程实现串口通信

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FPGA板上实现串口通信

    FPGA开发板上写的Verilog代码：
功能是从电脑端发送一个字节，然后把它接收回来。

`timescale 1ns / 10ps
`define Tgate 1

module uart_loop (osc,rst_,rxd,sdo,data_ready,framing_error,parity_error);

input osc ;
input rst_ ;

input rxd ;
output sdo ;

output data_ready ;
output framing_error ;
output parity_error ;

wire rst = ~rst_;
reg[7:0] oscd163r;
always @(posedge osc or posedge rst)
begin
if (rst)
oscd163r <= 0 ; 
else
oscd163r <= (oscd163r==8'HA3) ? 0 : (oscd163r + 1) ;
end

reg clk16x;
always @(posedge osc or posedge rst)
begin
if (rst)
clk16x <= 0 ; 
else
clk16x <= (oscd163r==8'HA3) ? ~clk16x : clk16x ;
end


reg[4:0] clk1d4r;
always @(posedge clk16x or posedge rst)
begin
if (rst)
clk1d4r = 5'b00000 ;
else 
clk1d4r = clk1d4r +1 ;
end
wire clk1d4 = clk1d4r[4];

wire data_ok = data_ready& ~framing_error & ~parity_error ;
wire tbre;//Status signal indication that the transmitter buffer register is empty
//CASE BRANCH
parameter IDLE = 3'h0,LOAD1 = 3'h1,LOAD2 = 3'h4, STORE=3'h2,WAIT_TX=3'h3 ;
reg[2:0] State;
always @(posedge clk1d4 or posedge rst)
  if(rst)
    State <= #`Tgate IDLE;
  else
    case(State)
    IDLE : 
      if(data_ok) 
        State <=  #`Tgate LOAD1;
      else
        State <=  #`Tgate IDLE;
    LOAD1 :
      State <= #`Tgate LOAD2;
    LOAD2 :
      State <= #`Tgate STORE;
    STORE : 
      State <= #`Tgate WAIT_TX;
    WAIT_TX :
      if(!tbre) 
        State <=  #`Tgate IDLE;
      else
        State <= #`Tgate WAIT_TX;
    default : State <= #`Tgate IDLE;
    endcase

reg rdn,wrn;
wire[7:0] dout;
reg[7:0] din;
//Execute
always @(posedge clk1d4 or posedge rst)
  if(rst)
    begin
      rdn <= #`Tgate 1'b1;
      wrn <= #`Tgate 1'b1;
      din <= #`Tgate 8'hEE;
    end
  else
    case(State)
    IDLE : 
      begin
      rdn <= #`Tgate 1'b1;
      wrn <= #`Tgate 1'b1;
      din <= #`Tgate 8'hEE;
      end
    LOAD1 :
      begin
      rdn <= #`Tgate 1'b0;
      wrn <= #`Tgate 1'b1;
      din <= #`Tgate 8'hEE;
      end
    LOAD2 :
      begin
      rdn <= #`Tgate 1'b0;
      wrn <= #`Tgate 1'b1;
      din <= #`Tgate dout;
      end
    STORE : 
      begin
      rdn <= #`Tgate 1'b1;
      wrn <= #`Tgate 1'b0;
      din <= #`Tgate din;
      end
    WAIT_TX :
      begin
      rdn <= #`Tgate 1'b1;
      wrn <= #`Tgate 1'b1;
      din <= #`Tgate 8'hEE;
      end
    default : 
      begin
      rdn <= #`Tgate 1'b1;
      wrn <= #`Tgate 1'b1;
      din <= #`Tgate 8'hEE;
      end
    endcase

uart i_uart(
dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn,din,tbre,tsre,wrn,sdo);

endmodule