代码搜索：FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/376804/9306008
bdf fpga_uartrw.bdf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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sof fpga_uartrw.sof
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qws fpga_uartrw.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
pt
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pof fpga_uartrw.pof
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qpf fpga_uartrw.qpf
# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
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pin fpga_uartrw.pin
-- Copyright (C) 1991-2007 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and a
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cdf fpga_uartrw.cdf
/* Quartus II Version 7.1 Build 156 04/30/2007 SJ Full Version */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EP2C8Q208) Path("D:/altera/71/jiangbi
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txt fpga测频.txt
module frequency(RD,WR,ad,lk,hk,CS,A,clk,freq,ALE,aout,int,clear);
input freq,clear,clk,RD,WR,ALE;
input [15:13] A;
input [4:1] hk;
inout [7:0] ad;
output [4:1] lk;
outpu
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vhd tb_fpga.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use std.textio.all;
use work.pack.all;
entity tb_sppe is
end tb_sppe;
archit
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vbp fpga串行通讯.vbp
Type=Exe
Form=主窗口.frm
Reference=*\G{00020430-0000-0000-C000-000000000046}#2.0#0#C:\WIN98\SYSTEM\STDOLE2.TLB#OLE Automation
Object={648A5603-2C6E-101B-82B6-000000000014}#1.1#0; MSCOMM32.OCX
Object=