tb_fpga.vhd

使用vhdl编写的一段程序。 主要功能是声音周期计算

  library ieee;
  use ieee.std_logic_1164.all;
  use ieee.std_logic_arith.all;
  use ieee.std_logic_signed.all;
  use std.textio.all;
  use work.pack.all;

  entity tb_sppe is
  end tb_sppe;

  architecture structural of tb_sppe is

    component sppe
      port (
        clk, rst : in  std_logic;
        adc      : in  input_type;
        en_read  : out std_logic;
        en_write : out std_logic;
        pp       : out std_logic_vector(7 downto 0)
        );        
    end component;

    signal rst      : std_logic := '0';
    signal clk      : std_logic := '0';
    signal adc      : input_type;
    signal pp       : std_logic_vector(7 downto 0);
    signal en_read  : std_logic;
    signal en_write : std_logic;

    constant DELAY : time := 0 us;
    
  begin  -- structural

  
    clk <= not(clk) after PULSEWIDTH;
    rst <= '1'      after RESET_TIME;
     
    DUT : sppe
      port map (
        clk      => clk,
        rst      => rst,
        adc      => adc,
        en_read  => en_read,
        en_write => en_write,
        pp       =>pp
    );

    -- Process that read and writes values from and to files.
    process (clk)
      file fin           : text is in INPUT_FILE;
      variable in_line   : line;
      variable in_value  : integer;
      file fout          : text is out OUTPUT_FILE;
      variable out_line  : line;
      variable out_value : integer;
      variable temp      : std_logic_vector(7 downto 0);
    begin
      if rising_edge(clk) then
        if rst = '0' then
          adc <= (others => '0');
        else
            if en_read ='1' then
               readline(fin, in_line);
               read(in_line, in_value);
               adc       <= conv_std_logic_vector (in_value, AD_WIDTH);
            end if;
            if en_write ='1' then
               temp      := pp;
               out_value := conv_integer (temp);
               write(out_line, out_value);
               writeline(fout, out_line);
            end if;
        
        end if;
      end if;
    end process;
   
  end structural;