代码搜索:FPGA加速
找到约 10,000 项符合「FPGA加速」的源代码
代码结果 10,000
www.eeworm.com/read/395930/2427111
cpp xlxram.cpp
/*
Simulation model of Xilinx FPGA BlockRAM memory
2002 A.S.Slusarczyk@tue.nl
*/
#include "xlxram.h"
//////////////////////////////////////////////////////////////////////////////////
// Dual-p
www.eeworm.com/read/395929/2431010
cpp xlxram.cpp
/*
Simulation model of Xilinx FPGA BlockRAM memory
2002 A.S.Slusarczyk@tue.nl
*/
#include "xlxram.h"
//////////////////////////////////////////////////////////////////////////////////
// Dual-p
www.eeworm.com/read/393024/2489877
vhd toplevel.vhd
-- AUTOGENERATED FILE! DO NOT EDIT --
--
-- ${outfile} created ${timestamp}
-- created from ${infile} by ${preprocessor}
-- This is the VHDL template for a top-level FPGA configuration
-- the follow
www.eeworm.com/read/393024/2490012
c bfload.c
/*************************************************************************
*
* bfload - loads xilinx bitfile into mesa 5i20 board FPGA
*
* Copyright (C) 2007 John Kasunich (jmkasunich at fastmail dot
www.eeworm.com/read/370579/9595056
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/415351/11075485
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/415351/11075555
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/268031/11156138
txt 加法器描述.txt
-- A Variety of Adder Styles
-- download from: www.fpga.com.cn & www.pld.com.cn
------------------------------------------------------------------------
-- Single-bit adder
-----------------------
www.eeworm.com/read/249157/12519159
v counter.v
//====================================================================
//
// copyright (c) 2007, Hisilicon Technologies Co.,Ltd
// All rights reserved.
//
// IP LIB INDEX: HIAVD FPGA
// IP Name
www.eeworm.com/read/121654/14744540
cpp 11.cpp
//Richardson外推加速法
#include
#include
#include
#include
const double x=1;
const double e=0.02;
const double E=0.00001;
using namespace std;
void main