toplevel.vhd

CNC 的开放码,EMC2 V2.2.8版

-- AUTOGENERATED FILE! DO NOT EDIT --
--
-- ${outfile} created ${timestamp}
-- created from ${infile} by ${preprocessor}

-- This is the VHDL template for a top-level FPGA configuration

-- the following lines are for the make system
-- they must start with three dashes or they will be ignored
--- device 2s200pq208-5
--- constraints 5i20-normal.ucf

library IEEE;
use IEEE.std_logic_1164.all;  -- defines std_logic types
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;

use work.businterface_pkg.all;
use work.configram_pkg.all;
${packages}

entity toplevel is
    -- the ports of this entity are physical FPGA pins
    port (
	-- local bus clock
	LCLK: in std_logic;
	-- local bus control signals --
	LW_R: in std_logic; 
	ADS: in std_logic; 
	BLAST: in std_logic; 
	READY: out std_logic; 
	INT: out std_logic;
	-- local address/data bus
	LAD: inout std_logic_vector (31 downto 0);
	-- the three 24 bit user pin ports
	IOBits: inout std_logic_vector (71 downto 0);
	-- led bits
	LEDS: inout std_logic_vector(7 downto 0)
    );
end toplevel;

architecture dataflow of toplevel is
	signal rd_bus : std_logic_vector ( 31 downto 0 );
	signal wr_bus : std_logic_vector ( 31 downto 0 );
	signal addr : std_logic_vector ( 15 downto 0 );
	signal read : std_logic;
	signal write : std_logic;
	signal next_addr : std_logic_vector ( 15 downto 0 );
	signal next_read : std_logic;
	signal next_write : std_logic;
${chipselect_signals}
	signal one : std_logic := '1';
	signal zero : std_logic := '0';
	signal pins_in : std_logic_vector (71 downto 0);
	signal pins_out : std_logic_vector (71 downto 0);
	signal pins_oe : std_logic_vector (71 downto 0);
	signal pins_invert : std_logic_vector (71 downto 0);
	signal pins_mode0 : std_logic_vector (71 downto 0);
	signal pins_mode1 : std_logic_vector (71 downto 0);

begin
    -- chip select logic (autogenerated)
${chipselect_logic}

busif: businterface
    port map (
	LAD => LAD,
	ADS => ADS,
	LW_R => LW_R,
	BLAST => BLAST,
	READY => READY,
	INT => int,
	rd_bus => rd_bus,
	wr_bus => wr_bus,
	addr => addr,
	read => read,
	write => write,
	next_addr => next_addr,
	next_read => next_read,
	next_write => next_write,
	clock => LCLK
    );

ram: configram
    port map (
	clock => LCLK,
	dout => rd_bus,
	din => wr_bus,
	addr => next_addr( 9 downto 2 ),
	rd => read,
	wr => write,
	ce => cs000000xxxxxxxx
    );


--    pindrivers: for pin_num in 71 downto 0 generate
--        pindriver: pindriver_core
--	port map (
--		pin => IOBits(pin_num),
--		input => pins_in(pin_num),
--		output => pins_out(pin_num),
--		outena => pins_oe(pin_num),
--		invert => pins_invert(pin_num),
--		mode0 => pins_mode0(pin_num),
--		mode1 => pins_mode1(pin_num)
--	);
--    end generate pindrivers;

-- module instances as defined in ${infile}
${instance_vhdl}

end dataflow;