代码搜索：FOSC
找到约 2,825 项符合「FOSC」的源代码
代码结果 2,825
www.eeworm.com/read/265642/11259280
jed fosc.jed
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v fosc.v
module fosc (clkx,clk,lddat,ldsel);
input clkx,clk;
output [7:0] lddat;
output [3:0] ldsel;
reg [23:0] count;
reg [15:0] min,min1;
reg [7:0] lddat_reg;
reg [3:0] ldsel_reg,ledbuf;
reg sec,fl
www.eeworm.com/read/265642/11259289
xst fosc.xst
set -tmpdir .
set -overwrite YES
run
-ifmt VERILOG
-top fosc
-p XC9500
-ifn fosc.prj
-opt_mode Speed
-opt_level 1
-check_attribute_syntax YES
-keep_hierarchy YES
-fsm_extract YES -fsm_encod
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ucf fosc.ucf
// Template UCF file created by the Project Navigator
NET clk LOC=P9;
NET clkx LOC=P10;
NET lddat LOC=P40;
NET lddat LOC=P41;
NET lddat LOC=P43;
NET lddat LOC=P44;
NET lddat LOC=P
www.eeworm.com/read/265642/11259298
npl fosc.npl
JDF E
// Created by ISE ver 1.0
PROJECT fosc
DESIGN fosc Normal
DEVKIT XC95108 PC84
DEVFAM xc9500
FLOW XST Verilog
MODULE fosc.v
MODSTYLE fosc Normal
[STRATEGY-LIST]
Normal=True, 103761567
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syr fosc.syr
Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s
--> Parameter overwrite set to YES
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ngd fosc.ngd
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rpt fosc.rpt
cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: fosc Date: 11-18-2002, 6:39PM
Device
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v fosc1.v
module fosc1 (clkx,clk,lddat,ldsel);
input clk,clkx;
output [7:0] lddat;
output [3:0] ldsel;
reg [22:0] count;
reg [15:0] min;
reg [7:0] lddat_reg;
reg [3:0] ldsel_reg,ledbuf;
reg sec;
al