📄 fosc.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: fosc Date: 11-18-2002, 6:39PM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
71 /108 ( 65%) 313 /540 ( 57%) 58 /108 ( 53%) 14 /69 ( 20%) 144/216 ( 66%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 0 0 | I/O : 12 51
Output : 12 12 | GCK/IO : 2 1
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 2 2 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 14 14
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 58
Non-registered Macrocell driving I/O 12
GLOBAL RESOURCES:
The complement of 'clk' mapped onto global clock net GCK1.
Signal 'clkx' mapped onto global clock net GCK2.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 71 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 71 macrocells used (MC).
End of Resource Summary
**************************** Errors and Warnings *************************
WARNING:Cpld - Unable to map all desired signals into function block, FB6,
because too many function block product terms are required. Buffering output
signal lddat<5> to allow all signals assigned to this function block to be
placed.
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
count_0 1 1 FB2_13 STD (b) (b)
count_1 1 1 FB4_10 STD (b) (b)
count_10 1 10 FB6_15 STD 55 I/O (b)
count_11 1 11 FB6_18 STD (b) (b)
count_12 1 12 FB6_14 STD 54 I/O (b)
count_13 1 13 FB6_13 STD (b) (b)
count_14 2 24 FB1_17 STD 13 I/O (b)
count_15 2 24 FB1_16 STD 12 GCK/I/O (b)
count_16 1 16 FB1_9 STD 6 I/O (b)
count_17 1 17 FB1_8 STD 5 I/O (b)
count_18 1 18 FB1_7 STD (b) (b)
count_19 2 24 FB1_15 STD 11 I/O (b)
count_2 3 24 FB1_18 STD (b) (b)
count_20 1 20 FB1_6 STD 4 I/O (b)
count_21 2 24 FB1_14 STD 10 GCK/I/O GCK
count_22 1 22 FB1_5 STD 3 I/O (b)
count_23 2 24 FB1_13 STD (b) (b)
count_3 2 24 FB1_12 STD 9 GCK/I/O GCK
count_4 2 24 FB1_11 STD 7 I/O (b)
count_5 2 24 FB1_10 STD (b) (b)
count_6 1 6 FB1_4 STD (b) (b)
count_7 1 7 FB6_10 STD (b) (b)
count_8 1 8 FB6_7 STD (b) (b)
count_9 1 9 FB6_4 STD (b) (b)
flag 1 1 FB5_3 STD 33 I/O (b)
lddat<0> 16 18 FB5_12 STD FAST 40 I/O O
lddat<1> 16 18 FB5_14 STD FAST 41 I/O O
lddat<2> 12 18 FB5_15 STD FAST 43 I/O O
lddat<3> 16 18 FB5_17 STD FAST 44 I/O O
lddat<4> 12 18 FB6_2 STD FAST 45 I/O O
lddat<5> 1 1 FB6_3 STD FAST 46 I/O O
lddat<5>_BUFR.MC 16 18 FB6_17 STD 56 I/O (b)
lddat<6> 12 18 FB6_5 STD FAST 47 I/O O
lddat<7> 0 0 FB6_6 STD FAST 48 I/O O
ldsel<0> 1 2 FB6_8 STD FAST 50 I/O O
ldsel<1> 1 2 FB6_9 STD FAST 51 I/O O
ldsel<2> 1 2 FB6_11 STD FAST 52 I/O O
ldsel<3> 1 2 FB6_12 STD FAST 53 I/O O
min1_0 3 6 FB5_6 STD 35 I/O (b)
min1_1 3 5 FB3_12 STD 23 I/O (b)
min1_10 11 14 FB3_2 STD 14 I/O (b)
min1_11 12 14 FB2_10 STD (b) (b)
min1_12 13 18 FB2_4 STD (b) (b)
min1_13 13 17 FB2_7 STD (b) (b)
min1_14 14 18 FB2_14 STD 81 I/O (b)
min1_15 15 18 FB2_18 STD (b) (b)
min1_2 3 6 FB3_11 STD 21 I/O (b)
min1_3 3 6 FB3_10 STD (b) (b)
min1_4 7 10 FB3_15 STD 25 I/O (b)
min1_5 7 9 FB3_13 STD (b) (b)
min1_6 8 10 FB2_11 STD 79 I/O (b)
min1_7 8 10 FB3_16 STD 26 I/O (b)
min1_8 10 14 FB3_18 STD (b) (b)
min1_9 10 13 FB5_8 STD 36 I/O (b)
min_0 2 4 FB5_5 STD 34 I/O (b)
min_1 2 4 FB3_9 STD 20 I/O (b)
min_10 2 4 FB3_8 STD 19 I/O (b)
min_11 2 4 FB3_7 STD (b) (b)
min_12 2 4 FB4_18 STD (b) (b)
min_13 2 4 FB4_17 STD 70 I/O (b)
min_14 2 4 FB4_16 STD (b) (b)
min_15 2 4 FB4_15 STD 69 I/O (b)
min_2 2 4 FB3_6 STD 18 I/O (b)
min_3 2 4 FB3_5 STD 17 I/O (b)
min_4 2 4 FB3_4 STD (b) (b)
min_5 2 4 FB3_3 STD 15 I/O (b)
min_6 2 4 FB4_14 STD 68 I/O (b)
min_7 2 4 FB4_13 STD (b) (b)
min_8 2 4 FB4_12 STD 67 I/O (b)
min_9 2 4 FB4_11 STD 66 I/O (b)
sec 1 24 FB1_3 STD 2 I/O (b)
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clk FB1_12 9 GCK/I/O GCK
clkx FB1_14 10 GCK/I/O GCK
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 16 24 24 26 0/0 12
FB2 7 19 19 76 0/0 12
FB3 15 21 21 66 0/0 12
FB4 9 19 19 17 0/0 11
FB5 8 31 31 76 4/0 11
FB6 16 30 30 52 8/0 11
---- ----- ----- -----
71 313 12/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 24/12
Number of signals used by logic mapping into function block: 24
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O
sec 1 0 0 4 FB1_3 STD 2 I/O (b)
count_6 1 0 0 4 FB1_4 STD (b) (b)
count_22 1 0 0 4 FB1_5 STD 3 I/O (b)
count_20 1 0 0 4 FB1_6 STD 4 I/O (b)
count_18 1 0 0 4 FB1_7 STD (b) (b)
count_17 1 0 0 4 FB1_8 STD 5 I/O (b)
count_16 1 0 0 4 FB1_9 STD 6 I/O (b)
count_5 2 0 0 3 FB1_10 STD (b) (b)
count_4 2 0 0 3 FB1_11 STD 7 I/O (b)
count_3 2 0 0 3 FB1_12 STD 9 GCK/I/O GCK
count_23 2 0 0 3 FB1_13 STD (b) (b)
count_21 2 0 0 3 FB1_14 STD 10 GCK/I/O GCK
count_19 2 0 0 3 FB1_15 STD 11 I/O (b)
count_15 2 0 0 3 FB1_16 STD 12 GCK/I/O (b)
count_14 2 0 0 3 FB1_17 STD 13 I/O (b)
count_2 3 0 0 2 FB1_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0 9: count_16.FBK.LFBK 17: count_23.FBK.LFBK
2: count_1 10: count_17.FBK.LFBK 18: count_3.FBK.LFBK
3: count_10 11: count_18.FBK.LFBK 19: count_4.FBK.LFBK
4: count_11 12: count_19.FBK.LFBK 20: count_5.FBK.LFBK
5: count_12 13: count_2.FBK.LFBK 21: count_6.FBK.LFBK
6: count_13 14: count_20.FBK.LFBK 22: count_7
7: count_14.FBK.LFBK 15: count_21.FBK.LFBK 23: count_8
8: count_15.FBK.LFBK 16: count_22.FBK.LFBK 24: count_9
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
sec XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_6 XX..........X....XXX.................... 6 6
count_22 XXXXXXXXXXXXXXX..XXXXXXX................ 22 22
count_20 XXXXXXXXXXXXX....XXXXXXX................ 20 20
count_18 XXXXXXXXXX..X....XXXXXXX................ 18 18
count_17 XXXXXXXXX...X....XXXXXXX................ 17 17
count_16 XXXXXXXX....X....XXXXXXX................ 16 16
count_5 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_4 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_3 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_23 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_21 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_19 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_15 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_14 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
count_2 XXXXXXXXXXXXXXXXXXXXXXXX................ 24 24
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 19/17
Number of signals used by logic mapping into function block: 19
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\5 0 FB2_1 (b) (b)
(unused) 0 0 0 5 FB2_2 71 I/O
(unused) 0 0 \/3 2 FB2_3 72 I/O (b)
min1_12 13 8<- 0 0 FB2_4 STD (b) (b)
(unused) 0 0 /\5 0 FB2_5 74 GSR/I/O (b)
(unused) 0 0 \/5 0 FB2_6 75 I/O (b)
min1_13 13 8<- 0 0 FB2_7 STD (b) (b)
(unused) 0 0 /\3 2 FB2_8 76 GTS/I/O (b)
(unused) 0 0 \/5 0 FB2_9 77 GTS/I/O (b)
min1_11 12 7<- 0 0 FB2_10 STD (b) (b)
min1_6 8 5<- /\2 0 FB2_11 STD 79 I/O (b)
(unused) 0 0 /\5 0 FB2_12 80 I/O (b)
count_0 1 0 \/4 0 FB2_13 STD (b) (b)
min1_14 14 9<- 0 0 FB2_14 STD 81 I/O (b)
(unused) 0 0 /\5 0 FB2_15 82 I/O (b)
(unused) 0 0 0 5 FB2_16 83 I/O
(unused) 0 0 \/5 0 FB2_17 84 I/O (b)
min1_15 15 10<- 0 0 FB2_18 STD (b) (b)
Signals Used by Logic in Function Block
1: count_0.FBK.LFBK 8: min1_13.FBK.LFBK 14: min1_5
2: flag 9: min1_14.FBK.LFBK 15: min1_6.FBK.LFBK
3: min1_0 10: min1_15.FBK.LFBK 16: min1_7
4: min1_1 11: min1_2 17: min1_8
5: min1_10 12: min1_3 18: min1_9
6: min1_11.FBK.LFBK 13: min1_4 19: sec
7: min1_12.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
min1_12 .XXXXXXXXXXXXXXXXXX..................... 18 18
min1_13 .XXXXXXX.XXXXXXXXXX..................... 17 17
min1_11 .XXXXX....XXXXXXXXX..................... 14 14
min1_6 .XXX......XXXXXX..X..................... 10 10
count_0 X....................................... 1 1
min1_14 .XXXXXXXXXXXXXXXXXX..................... 18 18
min1_15 .XXXXXXXXXXXXXXXXXX..................... 18 18
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
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