代码搜索：Detector
找到约 1,321 项符合「Detector」的源代码
代码结果 1,321
www.eeworm.com/read/160339/10542737
acf detector.acf
--
-- Copyright (C) 1988-1999 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any
www.eeworm.com/read/160339/10542742
cnf detector.cnf
www.eeworm.com/read/160339/10542748
vhd detector.vhd
library ieee;
use ieee.std_logic_1164.all;
entity detector is
port(clk,x:in std_logic;
z:out std_logic);
end detector;
architecture bhv of detector is
type states is(s0,s1,s
www.eeworm.com/read/422961/10598813
vhd detector.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity detector is
generic(
data_width:integer:=30; --输入输出数据宽度
thr:std_logic_vect
www.eeworm.com/read/351504/10644772
vhd detector.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;
-- 实体声明
entity detector is
port (
clk : in std_logic;
reset_n : in std_logic;
RxD : in std_logic;
new_data
www.eeworm.com/read/417873/10973043
bsf detector.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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vhd detector.vhd
-- 库声明
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use WORK.UART_PACKAGE.ALL;
-- 实体声明
entity detector is
port (
clk : in std_logic;
reset_n : in std_logic;
RxD : in std_logic;
new_data
www.eeworm.com/read/464869/7061551
v detector.v
module detector(clk,rst,rxd,new_data);
input clk,rst,rxd;
output new_data;
reg new_data;
reg lock;
always @(posedge clk or negedge rst)
if(!rst)
begin
new_
www.eeworm.com/read/170130/7102916
ldo detector.ldo
# Auto generated by Project Navigator for Modelsim
vlib work
vcom -93 -explicit detector.vhd
## You need to generate your own stimuli
vsim -t 1ps detector
view wave
add wave *
view structur