detector.vhd

来自「本程序实现8位序列检测的功能」· VHDL 代码 · 共 76 行

library ieee;
use ieee.std_logic_1164.all;

entity detector is
  port(clk,x:in  std_logic;
           z:out std_logic);
end detector;

architecture bhv of detector is
  type states is(s0,s1,s2,s3,s4,s5,s6,s7,s8);
  signal state:states;
begin 
  process(x,clk)
begin
if (clk'event and clk='1') then
     case state is
       when s0=>z<='0';
         if(x='1')then
           state<=s1;
         else
           state<=s0;
         end if;
       when s1=>z<='0';
         if(x='1')then
           state<=s2;
         else
           state<=s0;
         end if;
       when s2=>z<='0';
         if(x='1')then
           state<=s3;
         else
           state<=s0;
         end if;
       when s3=>z<='0';
         if(x='1')then
           state<=s4;
         else
           state<=s0;
         end if;
       when s4=>z<='0';
         if(x='1')then
           state<=s3;
         else
           state<=s5;
         end if;
       when s5=>z<='0';
         if(x='1')then
           state<=s1;
         else
           state<=s6;
         end if;
       when s6=>z<='0';
         if(x='1')then
           state<=s7;
         else
           state<=s0;
         end if;
       when s7=>z<='0';
         if(x='1')then
           state<=s2;
         else
           state<=s8;
         end if;
       when s8=>z<='1';
         if(x='1')then
           state<=s1;
         else
           state<=s0;
         end if;
       end case;
     end if;
   end process;
end bhv;