📄 detector.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity detector is
generic(
data_width:integer:=30; --输入输出数据宽度
thr:std_logic_vector(29 downto 0):="000000100111000100011110011000" --门限值
);
port(clk:in std_logic;
reset:in std_logic;
datain:in std_logic_vector(data_width-1 downto 0);
relation:out std_logic
);
end detector;
architecture behave of detector is
type sh_reg is array(4 downto 0) of signed(data_width-1 downto 0);
signal shift:sh_reg;
signal thre_hold_val:signed(29 downto 0);
signal sdatain:signed(data_width-1 downto 0);
signal srelation:std_logic;
signal ACQ_en:std_logic;
begin
sdatain<=signed(datain);
thre_hold_val<=signed(thr);
--选出最大值
process(reset,clk)
begin
if(reset='1')then
srelation<='0';
elsif(clk'event and clk='1')then
shift<=shift(3 downto 0) & sdatain;
if(shift(0)>thre_hold_val and shift(1)>thre_hold_val and shift(2)>thre_hold_val and shift(3)>thre_hold_val and shift(4)>thre_hold_val)then
if(shift(2)>shift(0) and shift(2)>=shift(1) and shift(2)>=shift(3) and shift(2)>shift(4))then
srelation<='1';
else
srelation<='0';
end if;
else
srelation<='0';
end if;
end if;
end process;
relation<=srelation;
end behave;
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