代码搜索结果

# Xilinx CORE Generator 6.1i # Username = Administrador # COREGenPath = C:\Winapp\Xilinx\coregen # ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen # ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen #

DESIGN cordic_tester VIEW behavioral.vhd GRAPHIC 1,0 0 0

Design Rules All the parameters relevant to the board and its manufacture are specified in the Design Rules. The layout can be checked any time with the aid of the Design Rule Check

function vtb5 % VTB5 % % VTB5_1 Transmissibility ratio of a SDOF system. % VTB5_2 Base excitation force transmissibility for a SDOF system. % VTB5_3 Normalized magnitude of the primary mass for absorb

Directory: \simulation This directory contains the vhdl testbench and the modelsim ini file for the SDR SDRAM controller reference design. The \work directory contains a precompiled library of

-- ================================================================================ -- (c) 2005 Altera Corporation. All rights reserved. -- Altera products are protected under numerous U.S. and fore

[Design Root] Version=1.0.0 [Directory] led_7.Sch=Sch [led_7.Sch] Editor Kind=Sch

Directory: \simulation This directory contains the verilog testbench and the modelsim ini file for the SDR SDRAM controller reference design. The \work directory contains a precompiled library

ISIS SCHEMATIC DESCRIPTION FORMAT 6.1 ===================================== Design: D:\Excise\Proteus\

Protel Design System Design Rule Check PCB File : PCB\GoHT_MB.PCB Date : 13-May-2007 Time : 18:35:23 WARNING: Split plane(s) intersect Keepout object(s) or board outline Internal