readme.txt

Altera 官方提供的SDRAM控制器,verilog的

Directory: \simulation

This directory contains the verilog testbench and the modelsim ini file for the 
SDR SDRAM controller reference design.  The \work directory contains a precompiled
library of the complete design.  In order to modify the design and re-simulate, simply
copy the source files from \source and \model into this directory and re-compile the
design.


If you wish to run the simulation using a clock frequency of 100mhz, you will
need to search the following files for "100mhz" and un-rem the 100mhz lines
and rem the 133mhz lines(as noted in the remarks in the individual files).


sdr_sdram_tb.v
mt48lc8m16a2.v
pll1.v
altclklock.v