image_package.vhd

Avalon_VGA

-- ================================================================================
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-- 
-- This reference design file, and your use thereof, is subject to and governed
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-- This reference design file is being provided on an "as-is" basis and as an
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-- warranties of merchantability, non-infringement, or fitness for a particular
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-- available, Altera expressly does not recommend, suggest or require that this
-- reference design file be used in combination with any other product not
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--================================================================================

-- This package provides vga timing details that can be used for
-- a 640x480 VGA driver.  This package is called by the vga_driver.vhd
-- file.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

PACKAGE image_package IS 
	CONSTANT hwidth			: integer := 794;
	CONSTANT vdepth			: integer := 528;
	CONSTANT line_width 	: integer := 640;
	CONSTANT number_lines	: integer := 480;
	
	-- blanking and sync pulse constants
	CONSTANT begin_hblank	: integer := 94+46;  -- 140
	CONSTANT end_hblank		: integer := 140+line_width;
	CONSTANT end_hsync		: integer := 94;
	
	CONSTANT begin_vblank	: integer := 2+32;  -- 34
	CONSTANT end_vblank		: integer := 34+number_lines;
	CONSTANT end_vsync		: integer := 2;	
END image_package; 

	
-- VGA Timing Information
--
-- Horizontal Timing
--
-- fvga = 25MHz
--
-- hblank --          -------------------------------------------           ------------
--          |_________|                                         |___________|
--          .         .                                         . .       . .
--          .         .<------------- 25.17 us ---------------->. .       . .
--          .         .<------------- 26.11 us ------------------>.       . .
--          .         .<------------- 29.88 us -------------------------->. .
--          .         .<------------- 31.77 us ---------------------------->.
--          .         .                                         . .       . .
-- hsync  ----      -----------------------------------------------       --------------
--           |______|                                             |_______|
--
--
-- We use a pixel counter to generate the hsync and hblank signals.  The counter should be reset
-- every 31.77 us and count each 1/25MHz period.  Therfore the counter will count 794 times.
--
-- From the timing diagram above the hblank off time is 6.6 us, using a 25MHz clock this
-- means the hblank off time is 165 counts.

-- The hsync off time is 3.77 us which corresponds to 94 counts.
-- 
-- The signals are generated using the following timing
--
-- hblank                                   --------  ...  -----------
--       ___________________________________|                        |_________
--
-- hsync ----------               ------------------  ...  -----------------
--		   |______________|                                        |____
-- 
--
-- count           0              94       140                      781  794,0
--
--
--
-- Vertical Timing
--
-- vblank --          -------------------------------------------           ------------
--          |_________|                                         |___________|
--          .         .                                         . .       . .
--          .         .<------------- 15.250 ms --------------->. .       . .
--          .         .<------------- 15.700 ms ----------------->.       . .
--          .         .<------------- 15.764 ms ------------------------->. .
--          .         .<------------- 16.784 ms --------------------------->.
--          .         .                                         . .       . .
-- vsync  ----      -----------------------------------------------       --------------
--           |______|                                             |_______|
--
-- 
-- The vertical timing is based on a line counter which increments every time
-- the pixel counter is reset to 0.
--
-- The vblank off time is 1.534 ms which is equivalent to transmitting 48 lines.
--
-- The vsync off time is 0.064 ms which is equivalent to transmitting 2 lines.
--
--
-- vblank -------                           --------  ...  -----------
--              |___________________________|                        |_________
--
-- vsync ----------      ---------------------------  ...  ------------------
--		   |_____|                                                   |____
-- 
--
-- linecount       0     2                 34                      514      528,0