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找到约 10,000 项符合「Design」的源代码

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www.eeworm.com/read/268284/11145497

txt readme_frac_resampler_dn_v2.txt

The fractional downsampler design in SysGen 9.1i is a fully parallel implementation of a fractional downsampler. The implementation has been designed in a general way so that it can be targeted to th
www.eeworm.com/read/413451/11155331

html bitcounter_waveforms.html

Sample Waveforms for bitcounter.vhd Sample behavioral waveforms for design file bitcounter.vhd The following waveforms
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txt readme.txt

Master MemoryExamples for MT32 v1.0.0 Readme file The design example shows how to interface Altera's 32-bit Master MegaCore functions to a synchronous memory similar to altsyncram. Please read the
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pin divider.pin

-- Copyright (C) 1991-2004 Altera Corporation -- Any megafunction design, and related netlist (encrypted or decrypted), -- support information, device programming or simulation file, and a
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vhd a8259_tst.vhd

-- Altera Microperipheral Reference Design Version 0802 --Copyright
www.eeworm.com/read/135779/13900133

m example52.m

%hf2 %============== %============== %define the problem... clc T=[+1 -1; -1 +1]; %design the network... [W,B]=solvehop(T);
www.eeworm.com/read/135779/13900424

m example55.m

%hf6 %============== %============== %define the problem... clc T=[+1 +1 -1 +1; -1 +1 +1 -1; -1 -1 -1 +1; +1 +1 +1 +1; -1 -1 +1 +1] %design the network... [W,B]=solvehop(T);
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m example52.m

%hf2 %============== %============== %define the problem... clc T=[+1 -1; -1 +1]; %design the network... [W,B]=solvehop(T);
www.eeworm.com/read/135754/13902558

m example55.m

%hf6 %============== %============== %define the problem... clc T=[+1 +1 -1 +1; -1 +1 +1 -1; -1 -1 -1 +1; +1 +1 +1 +1; -1 -1 +1 +1] %design the network... [W,B]=solvehop(T);
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html xpdesign.html

Xp Design Xp Design Our lead customer asked me yesterday, "In XP, who does the design?" I answered, "The team."