readme.txt

Master MemoryExamples for MT32 v1.0.0 Rtl core

Master MemoryExamples for MT32  v1.0.0 Readme file
The design example shows how to interface Altera's 32-bit Master MegaCore functions to a synchronous memory similar to altsyncram. 
Please read the information regarding this design example at
http://www.altera.com/support/example/exm-index.html, before using the example. 

This file contains the following information:
o  Package Contents
o  Software Tool Requirements
o  Release History
o  Contacting Altera

Package Contents
================
The zip file includes the following Verilog files
	o mem256x32.v     - 256x32 altsynram
	o lm_last.v            - Generates lm_lastn signal
	o mstr_mem32. v  - Top level user design
	o pmt32.v              - 32-bit PCI target
	o pmt32.vo            - Verilog functional simulation models for the PCI target
	o top_mt32.v          - Top level for this design example and instantiates the above 2 modules. 

Software Tool Requirements
==========================
	o Quartus II software version 4.2 or later 
	o PCI Compiler version 3.2.0 or later
Release History
================

Version 1.0.0
-------------
- First release of example.


Contacting Altera
=================

Although we have made every effort to ensure that this design example works 
correctly, there might be problems that we have not encountered. If you have 
a question or problem that is not answered by the information provided in this 
readme file or the example's documentation, please contact your Altera Field 
Applications Engineer.

If you have additional questions that are not answered in the documentation
provided with this function, please contact Altera Applications:

World-Wide Web:                 http://www.altera.com
                                http://www.altera.com/mysupport/
Technical Support Hotline:	(800) 800-EPLD (U.S.)
                                [phone] (Internationally)
                                
Copyright (c) 2002 Altera Corporation. All rights reserved.