readme_frac_resampler_dn_v2.txt

可变分数抽取器设计。用matlab里的sg实现

The fractional downsampler design in SysGen 9.1i is a fully parallel implementation of a fractional downsampler.
The implementation has been designed in a general way so that it can be targeted to the widest range of devices. 
However, with some small modifications, DSP48(E) blocks can be substituted for generic multipliers, adders, and accumulators
in the filter section of the design to obtain a higher performance version for Virtex-4 and Virtex-5 devices.


The design enables the input signal to be decimated by any fractional number between 1.0 and 128.0, inclusive. In fact, the
highest decimation rate can be increased to 1024 (by changing a parameter in the InitFcn call) without significantly
increasing required device resources.

The decimation rate is 128 (or max. decimation rate set by the parameter) divided by whatever value is present on the 'L' input
to the module. 'L' can be changed on the fly, which allows continously variable decimation rates.

The parameters of the design are set in the InitFcn callback in Model Properties and can be changed to adapt the design for
different input bit widths, coefficent bit widths, filter lengths, etc.