代码搜索：Decode
找到约 10,000 项符合「Decode」的源代码
代码结果 10,000
www.eeworm.com/read/18588/795010
v decode.v
module decode (binary,one_hot);
input [3:0] binary;
output[9:0] one_hot;
reg [9:0] one_hot;
always @(binary)
begin
case (binary)
4'b0001 : one_hot = 10'b0000000001; //1
4'b0010 : on
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spl decode.spl
[Inputs]
=binary[3:0]=
[Outputs]
=one_hot[9:0]=
[BiDir]
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sym decode.sym
VERSION 5
BEGIN SYMBOL
SYMBOLTYPE BLOCK
TIMESTAMP 2004 10 12 14 51 15
SYMPIN 0 -32 Input binary(3:0)
SYMPIN 384 -32 Output one_hot(9:0)
RECTANGLE N 64 -64 320 0
BEGIN DISPLAY 192 -72 ATTR Sym
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vhd decode.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decode is
Port ( binary : in std_logic_vector(3 downto 0);
one_hot : ou
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vhd decode.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decode is
Port ( binary : in std_logic_vector(3 downto 0);
one_hot : ou
www.eeworm.com/read/18588/795160
spl decode.spl
[Inputs]
=binary[3:0]=
[Outputs]
=one_hot[9:0]=
[BiDir]
www.eeworm.com/read/18588/795179
vhi decode.vhi
-- VHDL Instantiation Created from source file decode.vhd -- 18:13:42 12/19/2002
--
-- Notes:
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std
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sym decode.sym
VERSION 5
BEGIN SYMBOL
SYMBOLTYPE BLOCK
TIMESTAMP 2002 12 19 10 13 40
SYMPIN 0 -32 Input "binary(3:0)"
SYMPIN 384 -32 Output "one_hot(9:0)"
BEGIN DISPLAY 192 -72 ATTR "SymbolName"
ALIGNMEN
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vhd decode.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decode is
Port ( binary : in std_logic_vector(3 downto 0);
one_hot : ou