decode.vhi

FPGA-CPLD_DesignTool(8-9-10)源代码

-- VHDL Instantiation Created from source file decode.vhd -- 18:13:42 12/19/2002
--
-- Notes: 
-- 1) This instantiation template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the instantiated module
-- 2) To use this template to instantiate this entity, cut-and-paste and then edit

	COMPONENT decode
	PORT(
		binary : IN std_logic_vector(3 downto 0);          
		one_hot : OUT std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	Inst_decode: decode PORT MAP(
		binary => ,
		one_hot => 
	);