decode.sym

来自「FPGA-CPLD_DesignTool(8-9-10)源代码」· SYM 代码 · 共 24 行

VERSION 5
BEGIN SYMBOL 
SYMBOLTYPE BLOCK
TIMESTAMP 2004 10 12 14 51 15
SYMPIN 0 -32 Input binary(3:0)
SYMPIN 384 -32 Output one_hot(9:0)
RECTANGLE N 64 -64 320 0 
BEGIN DISPLAY 192 -72 ATTR SymbolName
    ALIGNMENT BCENTER
    FONT 56 "Arial"
END DISPLAY
LINE N 64 -32 0 -32 
BEGIN DISPLAY 72 -32 PIN binary(3:0) ATTR PinName
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 0 -44 64 -20 
LINE N 320 -32 384 -32 
BEGIN DISPLAY 312 -32 PIN one_hot(9:0) ATTR PinName
    ALIGNMENT RIGHT
    FONT 24 "Arial"
END DISPLAY
RECTANGLE N 320 -44 384 -20 
END SYMBOL