代码搜索：CycloneII
找到约 4,731 项符合「CycloneII」的源代码
代码结果 4,731
www.eeworm.com/read/370817/9583533
tdf altsyncram_igq1.tdf
--altsyncram ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE=
www.eeworm.com/read/370817/9583694
tdf altsyncram_mgq1.tdf
--altsyncram ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE=
www.eeworm.com/read/370817/9583974
tdf altsyncram_ngq1.tdf
--altsyncram ADDRESS_REG_B="CLOCK1" BYTE_SIZE=8 CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="NORMAL" CLOCK_ENABLE_INPUT_B="NORMAL" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE=
www.eeworm.com/read/317989/13491008
rpt dds_cordic_nativelink_simulation.rpt
Info: Start Nativelink Simulation process
========= EDA Simulation Settings =====================
Sim Mode : Gate
Family : cycloneii
Quartus root : d:/a
www.eeworm.com/read/304723/13788762
rpt test_nativelink_simulation.rpt
Info: Start Nativelink Simulation process
========= EDA Simulation Settings =====================
Sim Mode : Gate
Family : cycloneii
Quartus root : d:/a
www.eeworm.com/read/18141/776942
rpt test_nativelink_simulation.rpt
Info: Start Nativelink Simulation process
========= EDA Simulation Settings =====================
Sim Mode : Gate
Family : cycloneii
Quartus root : d:/a
www.eeworm.com/read/14659/401046
sxr mux.sxr
BeginView mux NoName
Inst: mux_out_3_0_c mux_out_3_0_c_cZ cycloneii_lcell_comb
Inst: mux_out_3_0 mux_out_3_0_cZ cycloneii_lcell_comb
Inst: en_in[1] en_in_1_ stratix_io
Inst: en_in[0]
www.eeworm.com/read/492760/1171488
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_ram_register is
generic(
width : integer := 1;
preset : integer := 0
);
port(
d
www.eeworm.com/read/466574/1510322
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_ram_register is
generic(
width : integer := 1;
preset : integer := 0
);
port(
d
www.eeworm.com/read/278121/4147759
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity cycloneii_ram_register is
generic(
width : integer := 1;
preset : integer := 0
);
port(
d