test_nativelink_simulation.rpt

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

Info: Start Nativelink Simulation process

========= EDA Simulation Settings =====================

Sim Mode              :  Gate
Family                :  cycloneii
Quartus root          :  d:/altera/quartus60/win/
Quartus sim root      :  d:/altera/quartus60/eda/sim_lib
Simulation Tool       :  modelsim
Simulation Language   :  verilog
Sim Output File       :  test.vo
Sim SDF file          :  test__verilog.sdo
Sim dir               :  simulation\modelsim

=======================================================

Info: Starting NativeLink simulation with ModelSim software
Sourced tool specific script -- d:/altera/quartus60/common/tcl/internal/nativelink/modelsim.tcl
Error: Gate Level Simulation Netlist not found -- run EDA NetList Writer to generate Gate Level simulation netlist
Error: NativeLink simulation flow was NOT successful



================The following additional information is provided to help identify the cause of error while running nativelink scripts=================
Nativelink TCL script failed with errorCode:  POSIX ENOENT {no such file or directory}
Nativelink TCL script failed with errorInfo:  couldn't open "D:/altera/quartus60/win/tclIndex": no such file or directory
    while executing
"open [file join $dir tclIndex]"