代码搜索：Controller
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www.eeworm.com/read/442041/7660914
vhd controller.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY controller IS
PORT (Hold, Reset, Clk : IN STD_LOGIC;
Num : IN Integer Range 0 To 49;
GA,GB,YA,YB,RA,RB :out STD_LOGIC
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bsf controller.bsf
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to
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v controller.v
//setup the definitions for the design
`define s0 4'd0 //reset (power on state)
`define s1 4'd1 //floor one
`define s2 4'd2 //floor two
`define s3 4'd3 //floor three
`define s4 4'd4 //floor four
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java controller.java
/**
*
*/
package hnu.software.pfdai;
import java.awt.GridLayout;
import java.awt.event.ActionEvent;
import java.awt.event.ActionListener;
import javax.swing.JFrame;
import javax.swing.J
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class controller.class
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qpf controller.qpf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu
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qws controller.qws
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
[ProjectWorkspace.Frames.ChildFrames.Document-0]
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vhd controller.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity controller is
port( clock : in std_logic; --输入时钟，频率为1Hz
reset : in std_logic; --复位信号，高电平有效
ho
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pof controller.pof
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qsf controller.qsf
# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any outpu