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-- ProjNav VHDL simulation template: control_unite_control_unite_test_vhd_tb.udo -- You may edit this file after the line that starts with -- '-- START' to customize your simulation -- START user-d

## NOTE: Do not edit this file. ## Autogenerated by ProjNav (creatfdo.tcl) on Wed Dec 20 13:43:31 中国标准时间 2006 ## vlib work vcom -93 -explicit control_unite.vhdl vcom -93 -explicit control_unit

Release 14.2 - xst P.28xd (nt) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to D:\_prj\Xilinx\Blog\Lab4\synthesis\xst_temp_dir\ Total REAL time to Xst completi

set -tmpdir D:\_prj\Xilinx\Blog\Lab4\synthesis\xst_temp_dir\ run -opt_mode speed -netlist_hierarchy as_optimized -opt_level 1 -p xc7z020clg484-1 -top system_processing_system7_0_wrapper -ifmt M

verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/b_atc.v verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK

Release 14.2 - xst P.28xd (nt) Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to D:\_prj\Xilinx\Blog\Lab3\synthesis\xst_temp_dir\ Total REAL time to Xst completi

set -tmpdir D:\_prj\Xilinx\Blog\Lab3\synthesis\xst_temp_dir\ run -opt_mode speed -netlist_hierarchy as_optimized -opt_level 1 -p xc7z020clg484-1 -top system_processing_system7_0_wrapper -ifmt M

verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/b_atc.v verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK