📄 system_processing_system7_0_wrapper_xst.prj

📁 自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

💻 PRJ

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verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/b_atc.v
verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/w_atc.v
verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/aw_atc.v
verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/atc.v
verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/processing_system7.v
verilog processing_system7_v4_01_a C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\processing_system7_v4_01_a/hdl/verilog/trace_buffer.v
verilog work ../hdl/system_processing_system7_0_wrapper.v

💿 文件大小 4436 K

👤 上传用户 angela5683

📂 所属分类可编程逻辑

🏷️ 相关标签

#ZedBoard #FPGA #ARM #访问

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