system_processing_system7_0_wrapper_xst.srp

自学ZedBoard：使用IP通过ARM PS访问FPGA（源代码）

Release 14.2 - xst P.28xd (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to D:\_prj\Xilinx\Blog\Lab3\synthesis\xst_temp_dir\


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.47 secs
 
--> 
TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input Format                       : MIXED
Input File Name                    : "system_processing_system7_0_wrapper_xst.prj"
Verilog Include Directory          : {"D:\_prj\Xilinx\Blog\Lab3\pcores\" "C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxBFMinterface\pcores\" "C:\Xilinx\14.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\" }

---- Target Parameters
Target Device                      : xc7z020clg484-1
Output File Name                   : "../implementation/system_processing_system7_0_wrapper.ngc"

---- Source Options
Top Module Name                    : system_processing_system7_0_wrapper

---- Target Options
Add IO Buffers                     : NO

---- General Options
Optimization Goal                  : speed
Netlist Hierarchy                  : as_optimized
Optimization Effort                : 1
Hierarchy Separator                : /

---- Other Options
Cores Search Directories           : {../implementation}

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/b_atc.v" into library processing_system7_v4_01_a
Parsing module <b_atc>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/w_atc.v" into library processing_system7_v4_01_a
Parsing module <w_atc>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/aw_atc.v" into library processing_system7_v4_01_a
Parsing module <aw_atc>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/atc.v" into library processing_system7_v4_01_a
Parsing module <atc>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" into library processing_system7_v4_01_a
Parsing module <processing_system7>.
Analyzing Verilog file "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/trace_buffer.v" into library processing_system7_v4_01_a
Parsing module <trace_buffer>.
Analyzing Verilog file "D:\_prj\Xilinx\Blog\Lab3\hdl\system_processing_system7_0_wrapper.v" into library work
Parsing module <system_processing_system7_0_wrapper>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <system_processing_system7_0_wrapper>.

Elaborating module <processing_system7(C_EN_EMIO_ENET0=0,C_EN_EMIO_ENET1=0,C_EN_EMIO_TRACE=0,C_INCLUDE_TRACE_BUFFER=0,C_TRACE_BUFFER_FIFO_SIZE=128,USE_TRACE_DATA_EDGE_DETECTOR=0,C_TRACE_BUFFER_CLOCK_DELAY=12,C_EMIO_GPIO_WIDTH=64,C_INCLUDE_ACP_TRANS_CHECK=0,C_USE_DEFAULT_ACP_USER_VAL=0,C_S_AXI_ACP_ARUSER_VAL=31,C_S_AXI_ACP_AWUSER_VAL=31,C_PS7_SI_REV="PRODUCTION",C_M_AXI_GP0_ID_WIDTH=12,C_M_AXI_GP0_ENABLE_STATIC_REMAP=0,C_M_AXI_GP1_ID_WIDTH=12,C_M_AXI_GP1_ENABLE_STATIC_REMAP=0,C_S_AXI_GP0_ID_WIDTH=6,C_S_AXI_GP1_ID_WIDTH=6,C_S_AXI_ACP_ID_WIDTH=3,C_S_AXI_HP0_ID_WIDTH=6,C_S_AXI_HP0_DATA_WIDTH=64,C_S_AXI_HP1_ID_WIDTH=6,C_S_AXI_HP1_DATA_WIDTH=64,C_S_AXI_HP2_ID_WIDTH=6,C_S_AXI_HP2_DATA_WIDTH=64,C_S_AXI_HP3_ID_WIDTH=6,C_S_AXI_HP3_DATA_WIDTH=64,C_M_AXI_GP0_THREAD_ID_WIDTH=12,C_M_AXI_GP1_THREAD_ID_WIDTH=12,C_NUM_F2P_INTR_INPUTS=1,C_FCLK_CLK0_BUF="TRUE",C_FCLK_CLK1_BUF="FALSE",C_FCLK_CLK2_BUF="FALSE",C_FCLK_CLK3_BUF="FALSE")>.

Elaborating module <BUFG>.

Elaborating module <PS7>.
WARNING:HDLCompiler:189 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 2374: Size mismatch in connection of port <SAXIHP1WACOUNT>. Formal port size is 6-bit while actual signal size is 8-bit.
WARNING:HDLCompiler:189 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 2390: Size mismatch in connection of port <SAXIHP2WACOUNT>. Formal port size is 6-bit while actual signal size is 8-bit.
WARNING:HDLCompiler:189 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 2494: Size mismatch in connection of port <FCLKCLKTRIGN>. Formal port size is 4-bit while actual signal size is 16-bit.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1015: Net <ENET0_GMII_COL_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1016: Net <ENET0_GMII_CRS_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1017: Net <ENET0_GMII_RX_DV_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1018: Net <ENET0_GMII_RX_ER_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1019: Net <ENET0_GMII_RXD_i[7]> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1024: Net <ENET1_GMII_COL_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1025: Net <ENET1_GMII_CRS_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1026: Net <ENET1_GMII_RX_DV_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1027: Net <ENET1_GMII_RX_ER_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1028: Net <ENET1_GMII_RXD_i[7]> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1035: Net <FTMD_TRACEIN_DATA_i[31]> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1036: Net <FTMD_TRACEIN_VALID_i> does not have a driver.
WARNING:HDLCompiler:634 - "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v" Line 1037: Net <FTMD_TRACEIN_ATID_i[3]> does not have a driver.
WARNING:HDLCompiler:189 - "D:\_prj\Xilinx\Blog\Lab3\hdl\system_processing_system7_0_wrapper.v" Line 1829: Size mismatch in connection of port <S_AXI_HP1_WACOUNT>. Formal port size is 8-bit while actual signal size is 6-bit.
WARNING:HDLCompiler:189 - "D:\_prj\Xilinx\Blog\Lab3\hdl\system_processing_system7_0_wrapper.v" Line 1875: Size mismatch in connection of port <S_AXI_HP2_WACOUNT>. Formal port size is 8-bit while actual signal size is 6-bit.
WARNING:HDLCompiler:189 - "D:\_prj\Xilinx\Blog\Lab3\hdl\system_processing_system7_0_wrapper.v" Line 2012: Size mismatch in connection of port <IRQ_F2P>. Formal port size is 16-bit while actual signal size is 1-bit.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <system_processing_system7_0_wrapper>.
    Related source file is "D:\_prj\Xilinx\Blog\Lab3\hdl\system_processing_system7_0_wrapper.v".
    Summary:
	no macro.
Unit <system_processing_system7_0_wrapper> synthesized.

Synthesizing Unit <processing_system7>.
    Related source file is "C:/Xilinx/14.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/processing_system7_v4_01_a/hdl/verilog/processing_system7.v".
        C_USE_DEFAULT_ACP_USER_VAL = 0
        C_S_AXI_ACP_ARUSER_VAL = 31
        C_S_AXI_ACP_AWUSER_VAL = 31
        C_M_AXI_GP0_THREAD_ID_WIDTH = 12
        C_M_AXI_GP1_THREAD_ID_WIDTH = 12
        C_M_AXI_GP0_ENABLE_STATIC_REMAP = 0
        C_M_AXI_GP1_ENABLE_STATIC_REMAP = 0
        C_M_AXI_GP0_ID_WIDTH = 12
        C_M_AXI_GP1_ID_WIDTH = 12
        C_S_AXI_GP0_ID_WIDTH = 6
        C_S_AXI_GP1_ID_WIDTH = 6
        C_S_AXI_HP0_ID_WIDTH = 6
        C_S_AXI_HP1_ID_WIDTH = 6
        C_S_AXI_HP2_ID_WIDTH = 6
        C_S_AXI_HP3_ID_WIDTH = 6
        C_S_AXI_ACP_ID_WIDTH = 3
        C_S_AXI_HP0_DATA_WIDTH = 64
        C_S_AXI_HP1_DATA_WIDTH = 64
        C_S_AXI_HP2_DATA_WIDTH = 64
        C_S_AXI_HP3_DATA_WIDTH = 64
        C_INCLUDE_ACP_TRANS_CHECK = 0
        C_NUM_F2P_INTR_INPUTS = 1
        C_FCLK_CLK0_BUF = "TRUE"
        C_FCLK_CLK1_BUF = "FALSE"
        C_FCLK_CLK2_BUF = "FALSE"
        C_FCLK_CLK3_BUF = "FALSE"
        C_EMIO_GPIO_WIDTH = 64
        C_INCLUDE_TRACE_BUFFER = 0
        C_TRACE_BUFFER_FIFO_SIZE = 128
        C_TRACE_BUFFER_CLOCK_DELAY = 12
        USE_TRACE_DATA_EDGE_DETECTOR = 0
        C_PS7_SI_REV = "PRODUCTION"
        C_EN_EMIO_ENET0 = 0
        C_EN_EMIO_ENET1 = 0
        C_EN_EMIO_TRACE = 0
WARNING:Xst:647 - Input <ENET0_GMII_RXD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET1_GMII_RXD> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_GP0_ARSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_GP0_AWSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_GP1_ARSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_GP1_AWSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP0_ARSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP0_AWSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP1_ARSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP1_AWSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP2_ARSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP2_AWSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP3_ARSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <S_AXI_HP3_AWSIZE<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IRQ_F2P<15:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FTMD_TRACEIN_DATA> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FTMD_TRACEIN_ATID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET0_GMII_COL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET0_GMII_CRS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET0_GMII_RX_DV> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET0_GMII_RX_ER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET1_GMII_COL> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET1_GMII_CRS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET1_GMII_RX_DV> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <ENET1_GMII_RX_ER> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FCLK_CLKTRIG3_N> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FCLK_CLKTRIG2_N> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FCLK_CLKTRIG1_N> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FCLK_CLKTRIG0_N> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FTMD_TRACEIN_VALID> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PS_SRSTB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PS_CLK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <PS_PORB> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ENET0_GMII_RXD_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ENET1_GMII_RXD_i> is used but never assigned. This sourceless signal will be automatically connected to value GND.