代码搜索：Control
找到约 10,000 项符合「Control」的源代码
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vhd mux_control.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_SIGNED.all;
entity mux_control is
generic (
stage : natural);
port (
clk : in std_lo
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tdf pll_control.tdf
--//////////////////////////////////////////////////////////////////////////////////////////////////////////// // 该电路为外部锁相环的控制电路；
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szr data_control.szr
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map data_control.map
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cel data_control.cel
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fse data_control.fse
fsm_encoding {5374371} onehot
fsm_state_encoding {5374371} init {000000000001}
fsm_state_encoding {5374371} waiting {000000000010}
fsm_state_encoding {5374371} st_rd_cha {000000000100}
f
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vif data_control.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file data
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ucf data_control.ucf
NET "clk" TNM_NET = "clk";
TIMESPEC "TS_clk" = PERIOD "clk" 2.5 ns HIGH 50 %;
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v data_control.v
module data_control (input clk,
input reset,
input [3:0] pn_lock_rd_clk,
input [7:0] rd_data_cha,
input [7:0] rd_data_chb,
input [7:0] rd_data_chc,
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