data_control.v

如何使用ISE和FPGA使用指南

module data_control (input clk,
		     input reset, 
		     input [3:0] pn_lock_rd_clk, 
		     input [7:0] rd_data_cha, 
		     input [7:0] rd_data_chb, 
		     input [7:0] rd_data_chc, 
		     input [7:0] rd_data_chd, 
		     output [3:0] rd, 
		     output [7:0] final_data, 
		     input [3:0] almost_full, 
		     input [3:0] almost_empty, 
		     input [3:0] full, 
		     input [3:0] empty, 
		     output [3:0] valid_ch, 
		     output [20:0] mac_cha, 
		     output [20:0] mac_chb, 
		     output [20:0] mac_chc, 
		     output [20:0] mac_chd, 
		     output [3:0] mac_dv);

    wire [3:0] 	  data_valid;
    wire 	  waiting_cntr_en, next_ch_en, dv_enable;
    wire [3:0] 	  next_ch;

    mac mac_inst
      (.clk(clk), 
       .reset(reset), 
       .rd_data_cha(rd_data_cha), 
       .rd_data_chb(rd_data_chb), 
       .rd_data_chc(rd_data_chc), 
       .rd_data_chd(rd_data_chd), 
       .data_valid(data_valid), 
       .mac_cha(mac_cha),
       .mac_chb(mac_chb), 
       .mac_chc(mac_chc), 
       .mac_chd(mac_chd), 
       .mac_dv(mac_dv),
       .dv_enable(dv_enable));

    data_output_mux data_output_mux_inst
      (.clk(clk), 
       .reset(reset), 
       .data_valid(data_valid), 
       .data_cha(rd_data_cha), 
       .data_chb(rd_data_chb), 
       .data_chc(rd_data_chc), 
       .data_chd(rd_data_chd), 
       .final_data(final_data), 
       .valid_ch(valid_ch),
       .dv_enable(dv_enable)); 

    read_ch_arbiter read_ch_arbiter_inst
      (.clk(clk), 
       .reset(reset), 
       .waiting_cntr_en(waiting_cntr_en), 
       .next_ch_en(next_ch_en), 
       .pn_lock_rd_clk(pn_lock_rd_clk), 
       .almost_full(almost_full), 
       .almost_empty(almost_empty),
       .full(full),
       .empty(empty),
       .next_ch(next_ch));

    data_control_fsm data_control_fsm_inst
      (.clk(clk), 
       .reset(reset), 
       .rd(rd), 
       .waiting_cntr_en(waiting_cntr_en), 
       .next_ch_en(next_ch_en), 
       .next_ch(next_ch), 
       .data_valid(data_valid),
       .dv_enable(dv_enable));   

endmodule // data_control