代码搜索：Control
找到约 10,000 项符合「Control」的源代码
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www.eeworm.com/read/486385/6540728
prj control_mem.prj
#
##-- Synplicity, Inc.
##-- Synplify version 7.3
##-- Project file control_mem.prj.
##-- Generated using ISE.
#implementation: control_mem
impl -add "control_mem"
##device options
proc fi
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srd control_mem.srd
f "noname"; #file 0
f "noname"; #file 1
f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 2
f "e:\vhdl\f8051\mc8051_p.vhd"; #file 3
f "d:\program files\synplicity\fpga_81\lib\vhd\std1
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msg control_mem.msg
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plg control_mem.plg
@P: Worst Slack : 981.389
@P: control_mem|clk - Estimated Frequency : 53.7 MHz
@P: control_mem|clk - Requested Frequency : 1.0 MHz
@P: control_mem|clk - Estimated Period : 18.611
@P: control_
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vhd control_mem.vhd
-------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.mc8051_p.all;
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vhd control_fsm.vhd
-------------------------------------------------------------------------------
library IEEE;
library work;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.mc8051_p.all;
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fse control_mem.fse
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vif control_mem.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file cont
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ncf control_mem.ncf
#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#
# Period Constraints
#Begin clock constraints
#End clock constraints
# Output Constraints
# Input Constraints
# I/O Regist