control_mem.ncf

8051VHDL原代码

#
# Constraints generated by Synplify Pro 8.1.0, Build 540R
#

# Period Constraints

#Begin clock constraints
#End clock constraints

# Output Constraints
# Input Constraints

# I/O Registers Packing Constraints
INST "s_int1_h1[0]" IOB=FALSE;
INST "s_int0_h1[0]" IOB=FALSE;
INST "s_ti_h1[0]" IOB=FALSE;
INST "s_tf1_h1[0]" IOB=FALSE;
INST "s_tf0_h1[0]" IOB=FALSE;
INST "s_ri_h1[0]" IOB=FALSE;
INST "all_trans_o[0]" IOB=FALSE;
INST "intblock_o" IOB=FALSE;
INST "all_wt_en_o[0]" IOB=FALSE;
INST "s_p0[1]" IOB=FALSE;
INST "s_p0[0]" IOB=FALSE;
INST "state[0]" IOB=TRUE;
INST "state[1]" IOB=TRUE;
INST "state[2]" IOB=TRUE;
INST "state[3]" IOB=FALSE;
INST "state[4]" IOB=TRUE;
INST "s_ir[7]" IOB=FALSE;
INST "s_ir[6]" IOB=FALSE;
INST "s_ir[5]" IOB=FALSE;
INST "s_ir[4]" IOB=FALSE;
INST "s_ir[3]" IOB=FALSE;
INST "s_ir[2]" IOB=FALSE;
INST "s_ir[1]" IOB=FALSE;
INST "s_ir[0]" IOB=FALSE;
INST "s_p2[0]" IOB=FALSE;
INST "s_p1[7]" IOB=FALSE;
INST "s_p1[6]" IOB=FALSE;
INST "s_p1[5]" IOB=FALSE;
INST "s_p1[4]" IOB=FALSE;
INST "s_p1[3]" IOB=FALSE;
INST "s_p1[2]" IOB=FALSE;
INST "s_p1[1]" IOB=FALSE;
INST "s_p1[0]" IOB=FALSE;
INST "s_p0[7]" IOB=FALSE;
INST "s_p0[6]" IOB=FALSE;
INST "s_p0[5]" IOB=FALSE;
INST "s_p0[4]" IOB=FALSE;
INST "s_p0[3]" IOB=FALSE;
INST "s_p0[2]" IOB=FALSE;
INST "s_p3[7]" IOB=FALSE;
INST "s_p3[6]" IOB=FALSE;
INST "s_p3[5]" IOB=FALSE;
INST "s_p3[4]" IOB=FALSE;
INST "s_p3[3]" IOB=FALSE;
INST "s_p3[2]" IOB=FALSE;
INST "s_p3[1]" IOB=FALSE;
INST "s_p3[0]" IOB=FALSE;
INST "s_p2[7]" IOB=FALSE;
INST "s_p2[6]" IOB=FALSE;
INST "s_p2[5]" IOB=FALSE;
INST "s_p2[4]" IOB=FALSE;
INST "s_p2[3]" IOB=FALSE;
INST "s_p2[2]" IOB=FALSE;
INST "s_p2[1]" IOB=FALSE;
INST "s_ext0isr_d" IOB=FALSE;
INST "s_ext0isrh_d" IOB=FALSE;
INST "s_ext1isr_d" IOB=FALSE;
INST "s_ext1isrh_d" IOB=FALSE;
INST "s_helpb" IOB=FALSE;
INST "s_inthigh" IOB=FALSE;
INST "s_intlow" IOB=FALSE;
INST "s_intpre2" IOB=FALSE;
INST "sbuf_0[7]" IOB=FALSE;
INST "sbuf_0[6]" IOB=FALSE;
INST "sbuf_0[5]" IOB=FALSE;
INST "sbuf_0[4]" IOB=FALSE;
INST "sbuf_0[3]" IOB=FALSE;
INST "sbuf_0[2]" IOB=FALSE;
INST "sbuf_0[1]" IOB=FALSE;
INST "sbuf_0[0]" IOB=FALSE;
INST "p0[0]" IOB=FALSE;
INST "p1[0]" IOB=FALSE;
INST "p2[0]" IOB=FALSE;
INST "p3[0]" IOB=FALSE;
INST "p0[1]" IOB=FALSE;
INST "p1[1]" IOB=FALSE;
INST "p2[1]" IOB=FALSE;
INST "p3[1]" IOB=FALSE;
INST "p0[2]" IOB=FALSE;
INST "p1[2]" IOB=FALSE;
INST "p2[2]" IOB=FALSE;
INST "p3[2]" IOB=FALSE;
INST "p0[3]" IOB=FALSE;
INST "p1[3]" IOB=FALSE;
INST "p2[3]" IOB=FALSE;
INST "p3[3]" IOB=FALSE;
INST "p0[4]" IOB=FALSE;
INST "p1[4]" IOB=FALSE;
INST "p2[4]" IOB=FALSE;
INST "p3[4]" IOB=FALSE;
INST "p0[5]" IOB=FALSE;
INST "p1[5]" IOB=FALSE;
INST "p2[5]" IOB=FALSE;
INST "p3[5]" IOB=FALSE;
INST "p0[6]" IOB=FALSE;
INST "p1[6]" IOB=FALSE;
INST "p2[6]" IOB=FALSE;
INST "p3[6]" IOB=FALSE;
INST "p0[7]" IOB=FALSE;
INST "p1[7]" IOB=FALSE;
INST "p2[7]" IOB=FALSE;
INST "p3[7]" IOB=FALSE;
INST "s_wt_0[1]" IOB=FALSE;
INST "s_wt_0[0]" IOB=FALSE;
INST "s_reload_0[7]" IOB=FALSE;
INST "s_reload_0[6]" IOB=FALSE;
INST "s_reload_0[5]" IOB=FALSE;
INST "s_reload_0[4]" IOB=FALSE;
INST "s_reload_0[3]" IOB=FALSE;
INST "s_reload_0[2]" IOB=FALSE;
INST "s_reload_0[1]" IOB=FALSE;
INST "s_reload_0[0]" IOB=FALSE;

# Location Constraints

# End of generated constraints