control_mem.prj

8051VHDL原代码

#
##-- Synplicity, Inc.
##-- Synplify version 7.3
##-- Project file control_mem.prj.
##-- Generated using ISE.

#implementation: control_mem
impl -add "control_mem"

##device options
proc findmatch {spec args} {  set arglist [join $args " "];  set idx [lsearch -glob $arglist $spec];  if {$idx != -1} {  return [lindex $arglist $idx];  } else {  return $spec;  }  }
			
proc findpackage {spec} { findmatch $spec [partdata -package [part]]}
proc findgrade   {spec} { findmatch $spec [partdata -grade   [part]]}
set_option -technology SPARTAN3
set_option -part xc3s200
set_option -package [findpackage {ft256}]
set_option -speed_grade [findgrade {-5}]

## Libraries


## Source files
add_file -verilog {d:/Program Files/Synplicity/fpga_81/bin/../lib/xilinx/unisim.v}
add_file {mc8051_p.vhd}
add_file {control_mem.vhd}

## Additional compile options
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -default_enum_encoding default
set_option -top_module control_mem
set_option -use_fsm_explorer 0

## Additional map options
set_option -frequency 0
set_option -fanout_limit 100
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -modular 0
set_option -retiming 0

## Additional simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

## Additional placeAndRoute options
set_option -write_apr_constraint 1

## Additional implAttr options
set_option -num_critical_paths 0
set_option -num_startend_points 0

set_option -vlog_std v2001
set_option -compiler_compatible 0

##--Set result format/file last
project -result_file {e:/vhdl/f8051/control_mem.edn}

##-- Constraint file
add_file -constraint {e:/vhdl/f8051/control_mem.sdc}