代码搜索：Control
找到约 10,000 项符合「Control」的源代码
代码结果 10,000
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plg control.plg
@P: Worst Slack : 1.920
@P: control|CLK48M - Estimated Frequency : 133.0 MHz
@P: control|CLK48M - Requested Frequency : 100.0 MHz
@P: control|CLK48M - Estimated Period : 7.521
@P: control|CLK
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srs control.srs
@E
@
#
#
#
# Created by Synplify Verilog HDL Compiler version 3.7, Build 090R from Synplicity, Inc.
# Copyright 1994-2006 Synplicity, Inc. , All rights reserved.
# Synthesis Netlist written on
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tlg control.tlg
Selecting top level module control
@N: CG364 :"C:\Actelprj\PWM\hdl\PWM_contr.v":2:7:2:13|Synthesizing module control
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areasrr control.areasrr
----------------------------------------------------------------------
Report for cell control.verilog
Cell usage:
cell
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srm control.srm
@E"VRMNFMl;C"RHyVDjCR
"VR8D:\HsLCF$\#MHbDV#$\$DMbH_V$UEn.\LDH\FbsNO#H\#VkH3FMPR";yDVHC
R4VOR":O\N0bCDsb[\IEl\8bD\IOl_FsM03;P"RHyVD.CR
qehv' RVHk#FhM3mA).3HbslR';yHRPCHIR8
Rjevhq VR'kF#HMm3X)b.3s'H
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sap control.sap
@ER
MI FsRMOF0DsFRsPCHoDF;o
HNR80(Nr:;j9
RNH3FODO" Rh mh"N;
HOR3D FO_oC8CsR"H"#C;H
NR#3N$_MOsCC#0MR":0s#"o;
b;RB
RNb3_H#OODF ;R4
RNb3FODO" Rh mh"N;
bOR3D FO_oC8CsR"H"#C;o
HFROkrM0.jd:9N;
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srd control.srd
f "noname"; #file 0
f "d:\libero\synplify\synplify_862h\lib\proasic\fusion.v"; #file 1
f "c:\actelprj\pwm\hdl\pwm_contr.v"; #file 2
VNAME 'work.control.verilog'; # view id 0
@EuyRsFCDN88CRsbN0HRDL
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sdf control.sdf
(DELAYFILE
(SDFVERSION "OVI 2.1")
(DESIGN "control")
(DATE "123")
(VENDOR "ProASIC3")
(PROGRAM "Synplify")
(VERSION "9.0.0, Build 368R")
(DIVIDER /)
(VOLTAGE 2.500000:2.500000:2.500000)
(PROC