代码搜索：Comp
找到约 10,000 项符合「Comp」的源代码
代码结果 10,000
www.eeworm.com/read/364157/9920119
xco buffer_comp.xco
# Xilinx CORE Generator 6.1i
# Username = Administrador
# COREGenPath = C:\Winapp\Xilinx\coregen
# ProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
# ExpandedProjectPath = E:\VHDL\PFCarrera\FPGA\Coregen
#
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xcp buffer_comp.xcp
# Xilinx CORE Generator 6.1i
SELECT Single_Port_Block_Memory Virtex2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET init_value = 0
CSET register_inputs = false
CSET write_enable_po
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vhd buffer_comp.vhd
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation,
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edn buffer_comp.edn
(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2004 10 9 1 3 47)
(author "Xilinx, Inc.")
(program "Xilinx CORE Generator" (version "Xilinx
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vho buffer_comp.vho
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation,
www.eeworm.com/read/167918/9947584
vhd top_comp.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package top_comp is
---------------------------------------------------------------------------------------------------
component sm_module
port(
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asm lsp_comp.asm
;==========================================================================
; File Name
; ----------
; LSP_COMP.ASM
;
; Brief Description of the Code:
; ------------------------------
; C
www.eeworm.com/read/167851/9949671
asm lsp_comp.asm
;==========================================================================
; File Name
; ----------
; LSP_COMP.ASM
;
; Brief Description of the Code:
; ------------------------------
; C
www.eeworm.com/read/167781/9952883
m comp_flat.m
function H = comp_flat(Hin,Q)
% Calculates cost function (overlapped ripple in passband)
% being minimized.
N = max(size(Hin));
M = floor(2048/Q); H = zeros(M,1);
for k=1:M
H(k) = abs(Hin(M -
www.eeworm.com/read/166544/10016693
vhd comp6.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY comp6 IS
PORT(
a0,a1,a2,a3,b0,b1,b2,b3,h0,h1,h2,h3: IN STD_LOGIC_VECTOR(3 down