comp6.vhd

来自「电子打铃器 在max plus 2 下编译通过」· VHDL 代码 · 共 37 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
ENTITY comp6 IS
	PORT(
		a0,a1,a2,a3,b0,b1,b2,b3,h0,h1,h2,h3: IN	STD_LOGIC_VECTOR(3 downto 0);
		clk:in std_logic;
		en:in std_logic;
		--sel:in std_logic_vector(2 downto 0);
		alm: OUT STD_LOGIC);
END comp6;

ARCHITECTURE a OF comp6 IS
signal tempalm:std_logic;	
BEGIN
	PROCESS (a0,a1,a2,a3,b0,b1,b2,b3)
		BEGIN
			IF (a0=b0 and a1=b1 and a2=b2 and a3=b3)or(a0=h0 and a1=h1 and a2=h2 and a3=h3) THEN
				tempalm<='1';
			ELSE
				tempalm<='0';
			END IF;
			
END PROCESS ;
process(clk)
		begin
			if clk'event and clk='1' then
			  if en='1' then
				alm<=tempalm;
		    	end if;
			end if;
end process;


END a;