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-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

-- Copyright (C) 1991-2005 Altera Corporation -- Your use of Altera Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any o

Assembler report for clock Wed Dec 14 14:45:26 2005 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2.

Fitter report for clock Wed Dec 14 14:45:24 2005 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Fi

module clock(clk,rst,dataout,en); input clk,rst; output[7:0] dataout; reg[7:0] dataout; output[7:0] en; reg[7:0] en; reg[3:0] dataout_buf[7:0]; reg[25:0] cnt; reg[15:0] cnt_scan; reg[3:0]

Timing Analyzer report for clock Wed Dec 14 14:45:28 2005 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice

Flow Status : Successful - Wed Dec 14 14:45:24 2005 Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version Revision Name : clock Top-level Entity Name : clock Family : MAX7000S Device : EP

Flow report for clock Wed Dec 14 14:45:28 2005 Version 5.0 Build 148 04/26/2005 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow

-------------------------------------------------------------------------------------- Timing Analyzer Summary --------------------------------------------------------------------------------------

Flow Status : Successful - Wed Dec 14 14:45:21 2005 Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version Revision Name : clock Top-level Entity Name : clock Family : MAX7000S Device : EP