clock.tan.summary

用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 34.000 ns
From           : en[1]~reg0
To             : dataout[0]
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 45.45 MHz ( period = 22.000 ns )
From           : cnt[19]
To             : cnt[9]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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