clock.map.summary

用verlog语言编的一个很好的综合实验,特别适合于FPGA/CPLD的初学者

Flow Status : Successful - Wed Dec 14 14:45:21 2005
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : clock
Top-level Entity Name : clock
Family : MAX7000S
Device : EPM7128SLC84-15
Timing Models : Final
Met timing requirements : N/A
Total macrocells : 95
Total pins : 18