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Clock 的代码
clock6.qpf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
clock6.hif
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
25
1264
OFF
OFF
OFF
OFF
OFF
FV_OFF
VRSM_ON
VHSM_ON
0
# entity
clock6
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case
clock6.qsf
# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any
clock_top.vhd
Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY clock_top IS
PORT(clk : IN STD_LOGIC; --全局时钟
keyvalue : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --按键值
isr_clock.s
/* isr_clock.s */
.globl _clock_isr
.align 4
_clock_isr:
/* save some registers */
pushl %eax
pushl %ds
pushl %es
pushl %fs
pushl %gs
/* set our descriptors up to a
clock_top.rpt
Project Information f:\ted\051226edaex\timevhd\clock_top.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 12/28/2005 23:32:30
Copyright (C) 1988-2002 Al
clock_top.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE Work.clock_v.all;
ENTITY clock_top IS
PORT(
clk,reset,set,model,clkdsp : IN STD_LOGIC;
daout
clock_v.hif
HIF003
--
-- Copyright (C) 1988-2000 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, an