clock_top.vhd

这是一些经典的vhdl example

Library IEEE ;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
ENTITY clock_top IS
	PORT(clk 				: IN STD_LOGIC;						--全局时钟
		 keyvalue			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);	--按键值
		 keypressed			: IN STD_LOGIC;                     --有按键来标志
		 functionkey		: IN STD_LOGIC;                     --是否是功能键
		 displaytime		: OUT STD_LOGIC_VECTOR(23 DOWNTO 0);--送显示时间
		 alarm_signal		: OUT STD_LOGIC;				    --蜂鸣器驱动	
		 alarmon 			: BUFFER STD_LOGIC;                 --闹钟开关标志     
		 houralarmon		: BUFFER STD_LOGIC);                --整点报时开关标志   
END clock_top;
ARCHITECTURE rtl OF clock_top IS
	--校时和设闹状态机
	COMPONENT statemachine
	PORT(clk 				: IN STD_LOGIC;						--全局时钟
		 keyvalue			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);	--按键值
		 keypressed			: IN STD_LOGIC;                     --有按键来标志
		 functionkey		: IN STD_LOGIC;                     --是否是功能键
		 buffertime			: BUFFER STD_LOGIC_VECTOR(23 DOWNTO 0);--缓存时间
		 iscount			: OUT STD_LOGIC;					--状态机状态是否是计数态
		 alarmload 			: OUT STD_LOGIC;                    --闹钟时间加载信号 
		 timeload			: OUT STD_LOGIC);                   --计时器时间加载信号
	END COMPONENT;
	--闹钟开关和整点报时开关状态机
	COMPONENT statemachine2
	PORT(clk 				: IN STD_LOGIC;						--全局时钟
		 keyvalue			: IN STD_LOGIC_VECTOR(3 DOWNTO 0);	--按键值
		 keypressed			: IN STD_LOGIC;                     --有按键来标志
		 alarmon 			: OUT STD_LOGIC;                    --闹钟时间加载信号 
		 houralarmon		: OUT STD_LOGIC);               --计时器时间加载信号
	END COMPONENT;
	--计时器
	COMPONENT counter
	PORT(clk 				: IN STD_LOGIC;							--全局时钟
		 load 				: IN STD_LOGIC;                         --同步加载信号
		 buffertime 		: IN STD_LOGIC_VECTOR(23 DOWNTO 0);     --同步加载数据
		 time				: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));   --当前时间输出
	END COMPONENT;
	--闹钟寄存器
	COMPONENT alarmreg
	PORT(alarmload 			: IN STD_LOGIC;							--并行加载的控制信号
		 clk				: IN STD_LOGIC;							--全局时钟
		 buffertime			: IN STD_LOGIC_VECTOR(23 DOWNTO 0);		--并行加载数据输入					
		 alarmtime			: OUT STD_LOGIC_VECTOR(23 DOWNTO 0));   --寄存器输出
	END COMPONENT;
	--闹铃管理模块
	COMPONENT bell
	PORT(					
		 alarmtime			: IN STD_LOGIC_VECTOR(23 DOWNTO 0);	--闹铃时间
		 time 				: IN STD_LOGIC_VECTOR(23 DOWNTO 0); --当前时间
		 alarmon			: IN STD_LOGIC;                     --闹钟开关状态
		 houralarmon		: IN STD_LOGIC;                     --整点报时开关状态
		 clk				: IN STD_LOGIC;                     --时钟
		 alarm_signal 		: OUT STD_LOGIC);                   --蜂鸣器驱动
	END COMPONENT;
	--校时和设闹状态机的输出
	SIGNAL buffertime       : STD_LOGIC_VECTOR(23 DOWNTO 0);
	SIGNAL iscount 			: STD_LOGIC;
	SIGNAL alarmload 		: STD_LOGIC;
	SIGNAL timeload			: STD_LOGIC;
    --当前时间
	SIGNAL time      		: STD_LOGIC_VECTOR(23 DOWNTO 0);
    --闹钟时间
	SIGNAL alarmtime      	: STD_LOGIC_VECTOR(23 DOWNTO 0);
BEGIN
	--校时和设闹状态机
	sm1: statemachine 
		PORT MAP (clk => clk,
				  keyvalue => keyvalue,
				  keypressed => keypressed,
				  functionkey => functionkey,
				  buffertime => buffertime,
				  iscount => iscount,
				  alarmload => alarmload,
				  timeload => timeload);
	--闹钟开关和整点报时开关状态机
	sm2: statemachine2
		PORT MAP (clk => clk,
				  keyvalue => keyvalue,
				  keypressed => keypressed,
				  alarmon => alarmon,
				  houralarmon => houralarmon);
	--计时器
	cnt: counter
		PORT MAP (clk => clk,
				  load => timeload,
				  buffertime => buffertime,
				  time => time);
	--闹钟寄存器
	reg: alarmreg
		PORT MAP (clk => clk,
				  alarmload => alarmload,
				  buffertime => buffertime,
				  alarmtime => alarmtime);
	--闹铃管理模块
	bl: bell
		PORT MAP (clk => clk,
				  alarmtime => alarmtime,
				  time => time,
				  alarmon => alarmon,
				  houralarmon => houralarmon,
				  alarm_signal => alarm_signal);
	--多路选通器
	PROCESS(iscount,time,buffertime)
	BEGIN
		IF(iscount='1')THEN
			displaytime <= time;
		ELSE
			displaytime <= buffertime;
		END IF;
	END PROCESS;
END rtl;