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Clock 的代码
clock_gen.v
module CLOCK_GEN ( CLK, RESETN, INT_CLK );
input CLK;
input RESETN;
output INT_CLK;
reg COUNT;
reg INT_CLK;
always @ (posedge CLK or negedge RESETN)
begin
if (RESETN == 0)
begin
CO
clock_gen.vhd
--------------------------------------------------
-- FREQUENCY DIVIDER -----------------------------
--
-- File: CLOCK_GEN.vhd
-- Task: Divide system clock by 2.
-------------------------------------
clock_gen.v
module CLOCK_GEN ( CLK, RESETN, TEST_MODE, INT_CLK );
input CLK;
input RESETN;
input TEST_MODE;
output INT_CLK;
reg COUNT;
reg INT_CLK;
reg DIV_CLK;
always @ (posedge CLK or negedge RESETN)
begin
clock_gen.vhd
--------------------------------------------------
-- FREQUENCY DIVIDER -----------------------------
--
-- File: CLOCK_GEN.vhd
-- Task: Divide system clock by 2.
-------------------------------------
clock_gen.v
module CLOCK_GEN ( CLK, RESETN, INT_CLK );
input CLK;
input RESETN;
output INT_CLK;
reg COUNT;
reg INT_CLK;
always @ (posedge CLK or negedge RESETN)
begin
if (RESETN == 0)
begin
CO
clock_gen.vhd
--------------------------------------------------
-- FREQUENCY DIVIDER -----------------------------
--
-- File: CLOCK_GEN.vhd
-- Task: Divide system clock by 2.
-------------------------------------
clock_gen.vhd
--------------------------------------------------
-- FREQUENCY DIVIDER -----------------------------
--
-- File: CLOCK_GEN.vhd
-- Task: Divide system clock by 2.
-------------------------------------
clock_gen.v
module CLOCK_GEN ( CLK, RESETN, TEST_MODE, INT_CLK );
input CLK;
input RESETN;
input TEST_MODE;
output INT_CLK;
reg COUNT;
reg INT_CLK;
reg DIV_CLK;
always @ (posedge CLK or negedge RESETN)
begin
clock.db_info
Quartus_Version = Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Web Edition
Version_Index = 134276865
Creation_Time = Thu Aug 07 09:55:28 2008