clock_gen.vhd

来自「design compile synthesis user guide」· VHDL 代码 · 共 53 行

--------------------------------------------------
-- FREQUENCY DIVIDER -----------------------------
--
-- File: CLOCK_GEN.vhd
-- Task: Divide system clock by 2.
--------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity CLOCK_GEN is
  port( CLK:in      STD_LOGIC;
        RESETN:in   STD_LOGIC;
        TEST_MODE:in   STD_LOGIC;
        INT_CLK:out STD_LOGIC
  );
end CLOCK_GEN;


architecture RTL of CLOCK_GEN is

signal COUNT : STD_LOGIC;
signal DIV_CLK : STD_LOGIC;

begin
  DIVIDER: process (CLK, RESETN)  begin
    if (RESETN = '0') then
       COUNT <= '0';
       DIV_CLK <= '0';
    elsif (CLK'event and CLK = '1') then
       if (COUNT = '1') then
         COUNT <= '0';
         DIV_CLK <= '1';
       else
         COUNT <= '1';
         DIV_CLK <= '0';
       end if;
    end if;
  end process DIVIDER;

  Test : Process (TEST_MODE, CLK, DIV_CLK) 
     begin
     if (TEST_MODE = '1') then
        INT_CLK <= CLK;
     else
        INT_CLK <= DIV_CLK;
     end if;
  end process;

end RTL;