clock_gen.v

来自「design compile synthesis user guide」· Verilog 代码 · 共 40 行

module CLOCK_GEN ( CLK, RESETN, TEST_MODE, INT_CLK );

input  CLK;
input RESETN;
input TEST_MODE;
output INT_CLK;

reg COUNT;
reg INT_CLK;
reg DIV_CLK;

always @ (posedge CLK or negedge RESETN)
begin
    if (RESETN == 0)
      begin
      COUNT <= 0;
      DIV_CLK <= 0;
      end
    else if (COUNT == 1) 
      begin
      COUNT <= 0;
      DIV_CLK <= 1;
      end
    else
      begin
      COUNT <= 1;
      DIV_CLK <= 0;
      end
end

always @(TEST_MODE or CLK or DIV_CLK)
begin
    if (TEST_MODE)
       INT_CLK <= CLK;
    else
       INT_CLK <= DIV_CLK;
end

endmodule