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Clock 的代码
clock.vhdsim_synth
CLOCK.vhdsim_synth -- generated only for ProjNav status tracking
Simulation Model Target: ModelSim SE (VHDL)
clock_synthesis.vhd
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-- Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.
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clock_summary.html
Xilinx Implementation Summary
Design Overview
clock_opt.bak
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.a*; *.src)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
clock.uv2
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (Target 1), 0x0000 // Tools: 'MCS-51'
Group (os)
Group (user)
Group (Target CPU)
Group (pcf8563)
Group (key)
Group (iic)
tz_clock.c
#include
#include
#include
#define uchar unsigned char
#define uint unsigned int
#define RAM62256 0x8000/*外部RAM寄存器的地址*/
#define COM8279 XBYTE[0x6100]/*8279命令/状态
clock.map.rpt
Analysis & Synthesis report for clock
Fri Oct 27 22:10:47 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
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; Table of Contents ;
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1. Legal N
clock.fit.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
clock.map.eqn
-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any o
clock.asm.rpt
Assembler report for clock
Fri Oct 27 22:10:54 2006
Version 5.0 Build 148 04/26/2005 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2.