clock_synthesis.vhd

XLINX做的数字钟

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: H.38
--  \   \         Application: netgen
--  /   /         Filename: CLOCK_synthesis.vhd
-- /___/   /\     Timestamp: Mon Jun 23 21:42:47 2008
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command: -intstyle ise -ar Structure -w -ofmt vhdl -sim CLOCK.ngc CLOCK_synthesis.vhd 
-- Device: xcv100-4-pq240
-- Design Name: CLOCK
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Verification Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

entity CLOCK is
  port (
    CLR : in STD_LOGIC := 'X'; 
    SET1 : in STD_LOGIC := 'X'; 
    CP : in STD_LOGIC := 'X'; 
    ALMSETH : in STD_LOGIC := 'X'; 
    ALMSETM : in STD_LOGIC := 'X'; 
    ALMCLR : in STD_LOGIC := 'X'; 
    PAUSE : in STD_LOGIC := 'X'; 
    MSETUP : in STD_LOGIC := 'X'; 
    HSETUP : in STD_LOGIC := 'X'; 
    MH0 : out STD_LOGIC; 
    MH1 : out STD_LOGIC; 
    MH2 : out STD_LOGIC; 
    MH3 : out STD_LOGIC; 
    ALARMOUT : out STD_LOGIC; 
    ML0 : out STD_LOGIC; 
    ML1 : out STD_LOGIC; 
    ML2 : out STD_LOGIC; 
    ML3 : out STD_LOGIC; 
    HH0 : out STD_LOGIC; 
    HH1 : out STD_LOGIC; 
    HH2 : out STD_LOGIC; 
    HH3 : out STD_LOGIC; 
    HL0 : out STD_LOGIC; 
    HL1 : out STD_LOGIC; 
    HL2 : out STD_LOGIC; 
    HL3 : out STD_LOGIC; 
    SH0 : out STD_LOGIC; 
    SH1 : out STD_LOGIC; 
    SH2 : out STD_LOGIC; 
    SH3 : out STD_LOGIC; 
    SL0 : out STD_LOGIC; 
    SL1 : out STD_LOGIC; 
    SL2 : out STD_LOGIC; 
    SL3 : out STD_LOGIC 
  );
end CLOCK;

architecture Structure of CLOCK is
  signal CLR_IBUF : STD_LOGIC; 
  signal MH0_OBUF : STD_LOGIC; 
  signal MH1_OBUF : STD_LOGIC; 
  signal MH2_OBUF : STD_LOGIC; 
  signal MH3_OBUF : STD_LOGIC; 
  signal ALARMOUT_OBUF : STD_LOGIC; 
  signal SET1_IBUF : STD_LOGIC; 
  signal CP_BUFGP : STD_LOGIC; 
  signal ML0_OBUF : STD_LOGIC; 
  signal ML1_OBUF : STD_LOGIC; 
  signal ML2_OBUF : STD_LOGIC; 
  signal ML3_OBUF : STD_LOGIC; 
  signal HH0_OBUF : STD_LOGIC; 
  signal HH1_OBUF : STD_LOGIC; 
  signal HH2_OBUF : STD_LOGIC; 
  signal HH3_OBUF : STD_LOGIC; 
  signal ALMSETH_IBUF : STD_LOGIC; 
  signal ALMSETM_IBUF : STD_LOGIC; 
  signal ALMCLR_IBUF : STD_LOGIC; 
  signal HL0_OBUF : STD_LOGIC; 
  signal HL1_OBUF : STD_LOGIC; 
  signal HL2_OBUF : STD_LOGIC; 
  signal HL3_OBUF : STD_LOGIC; 
  signal PAUSE_IBUF : STD_LOGIC; 
  signal MSETUP_IBUF : STD_LOGIC; 
  signal HSETUP_IBUF : STD_LOGIC; 
  signal SH0_OBUF : STD_LOGIC; 
  signal SH1_OBUF : STD_LOGIC; 
  signal SH2_OBUF : STD_LOGIC; 
  signal SH3_OBUF : STD_LOGIC; 
  signal SL0_OBUF : STD_LOGIC; 
  signal SL1_OBUF : STD_LOGIC; 
  signal SL2_OBUF : STD_LOGIC; 
  signal SL3_OBUF : STD_LOGIC; 
  signal XLXN_1 : STD_LOGIC; 
  signal XLXN_4 : STD_LOGIC; 
  signal XLXN_7 : STD_LOGIC; 
  signal XLXN_9 : STD_LOGIC; 
  signal PHOUR : STD_LOGIC; 
  signal XLXN_11 : STD_LOGIC; 
  signal CLOCK : STD_LOGIC; 
  signal XLXN_13 : STD_LOGIC; 
  signal XLXN_20 : STD_LOGIC; 
  signal XLXN_15 : STD_LOGIC; 
  signal PS : STD_LOGIC; 
  signal PM : STD_LOGIC; 
  signal XLXI_2_XLXN_2 : STD_LOGIC; 
  signal XLXI_2_XLXN_13 : STD_LOGIC; 
  signal XLXI_2_XLXN_3 : STD_LOGIC; 
  signal XLXI_1_XLXN_2 : STD_LOGIC; 
  signal XLXI_1_XLXN_13 : STD_LOGIC; 
  signal XLXI_1_XLXN_3 : STD_LOGIC; 
  signal XLXI_3_XLXN_31 : STD_LOGIC; 
  signal XLXI_3_XLXN_38 : STD_LOGIC; 
  signal XLXI_3_XLXN_37 : STD_LOGIC; 
  signal XLXI_3_XLXN_39 : STD_LOGIC; 
  signal XLXI_3_CLR1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_CLR1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXN_39 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXN_37 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXN_38 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXN_31 : STD_LOGIC; 
  signal XLXI_9_HH3 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXN_13 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXN_3 : STD_LOGIC; 
  signal XLXI_9_HH2 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXN_2 : STD_LOGIC; 
  signal XLXI_9_HLO2 : STD_LOGIC; 
  signal XLXI_9_HLO1 : STD_LOGIC; 
  signal XLXI_9_HLO0 : STD_LOGIC; 
  signal XLXI_9_HL3 : STD_LOGIC; 
  signal XLXI_9_HL2 : STD_LOGIC; 
  signal XLXI_9_HL1 : STD_LOGIC; 
  signal XLXI_9_HL0 : STD_LOGIC; 
  signal XLXI_9_MHO3 : STD_LOGIC; 
  signal XLXI_9_MHO2 : STD_LOGIC; 
  signal XLXI_9_MHO1 : STD_LOGIC; 
  signal XLXI_9_MHO0 : STD_LOGIC; 
  signal XLXI_9_MLO0 : STD_LOGIC; 
  signal XLXI_9_MLO1 : STD_LOGIC; 
  signal XLXI_9_MLO2 : STD_LOGIC; 
  signal XLXI_9_MLO3 : STD_LOGIC; 
  signal XLXI_9_MH0 : STD_LOGIC; 
  signal XLXI_9_MH1 : STD_LOGIC; 
  signal XLXI_9_MH2 : STD_LOGIC; 
  signal XLXI_9_MH3 : STD_LOGIC; 
  signal XLXI_9_ML0 : STD_LOGIC; 
  signal XLXI_9_ML1 : STD_LOGIC; 
  signal XLXI_9_ML2 : STD_LOGIC; 
  signal XLXI_9_ML3 : STD_LOGIC; 
  signal XLXI_9_HHO0 : STD_LOGIC; 
  signal XLXI_9_HHO1 : STD_LOGIC; 
  signal XLXI_9_HHO2 : STD_LOGIC; 
  signal XLXI_9_HHO3 : STD_LOGIC; 
  signal XLXI_9_HLO3 : STD_LOGIC; 
  signal XLXI_9_HH0 : STD_LOGIC; 
  signal XLXI_9_HH1 : STD_LOGIC; 
  signal CLOCK1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_2_TC : STD_LOGIC; 
  signal XLXI_3_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_3_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_3_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_3_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_2_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_2_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_2_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_2_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_2_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_1_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_1_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_1_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_1_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_1_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_2_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_2_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_2_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_2_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_2_XLXI_2_TC : STD_LOGIC; 
  signal XLXI_1_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_1_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_1_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_1_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_1_XLXI_2_TC : STD_LOGIC; 
  signal XLXI_3_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_3_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_3_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_3_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_3_XLXI_2_TC : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_OX3 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_AO3A : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_A03B : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_AX2 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_D3 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_D2 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_D1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_D0 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_AX1 : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_CEO : STD_LOGIC; 
  signal XLXI_9_XLXI_2_XLXI_1_TC : STD_LOGIC; 
  signal XLXI_9_XLXI_30_C2 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_C1 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_C0 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_CIN : STD_LOGIC; 
  signal XLXI_9_XLXI_30_XLXN_1 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_S3 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_S2 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_S1 : STD_LOGIC; 
  signal XLXI_9_XLXI_30_S0 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_OX3 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_AO3A : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_A03B : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_AX2 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_D3 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_D2 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_D1 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_D0 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_AX1 : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_CEO : STD_LOGIC; 
  signal XLXI_9_XLXI_1_XLXI_2_TC : STD_LOGIC; 
  signal NLW_XLXI_9_XLXI_1_XLXI_7_O_UNCONNECTED : STD_LOGIC; 
begin
  XLXI_15 : FDC
    generic map(
      INIT => '0'
    )
    port map (
      D => XLXN_20,
      CLR => CLR_IBUF,
      C => CLOCK,
      Q => PHOUR
    );
  XLXI_14 : INV
    port map (
      I => ALMSETM_IBUF,
      O => XLXN_15
    );
  XLXI_13 : INV
    port map (
      I => ALMCLR_IBUF,
      O => XLXN_13
    );
  XLXI_12 : INV
    port map (
      I => ALMSETH_IBUF,
      O => XLXN_11
    );
  XLXI_11 : INV
    port map (
      I => MSETUP_IBUF,
      O => XLXN_9
    );
  XLXI_10 : INV
    port map (
      I => HSETUP_IBUF,
      O => XLXN_7
    );
  XLXI_8 : OR2
    port map (
      I0 => PAUSE_IBUF,
      I1 => CP_BUFGP,
      O => CLOCK1
    );
  XLXI_6 : AND2
    port map (
      I0 => PS,
      I1 => PM,
      O => XLXN_20
    );
  XLXI_5 : OR2
    port map (
      I0 => XLXN_7,
      I1 => PHOUR,
      O => XLXN_4
    );
  XLXI_4 : OR2
    port map (
      I0 => XLXN_9,
      I1 => PS,
      O => XLXN_1
    );
  XLXI_2_XLXI_7 : AND5b2
    port map (
      I0 => MH3_OBUF,
      I1 => MH1_OBUF,
      I2 => MH2_OBUF,
      I3 => MH0_OBUF,
      I4 => XLXI_2_XLXN_13,
      O => PM
    );
  XLXI_2_XLXI_5 : OR2
    port map (
      I0 => XLXI_2_XLXN_3,
      I1 => CLR_IBUF,
      O => XLXI_2_XLXN_2
    );
  XLXI_2_XLXI_4 : AND4b2
    port map (
      I0 => MH3_OBUF,
      I1 => MH0_OBUF,
      I2 => MH2_OBUF,
      I3 => MH1_OBUF,
      O => XLXI_2_XLXN_3
    );
  XLXI_2_XLXI_3 : AND4b2
    port map (
      I0 => ML2_OBUF,
      I1 => ML1_OBUF,
      I2 => ML3_OBUF,
      I3 => ML0_OBUF,
      O => XLXI_2_XLXN_13
    );
  XLXI_1_XLXI_7 : AND5b2
    port map (
      I0 => SH3_OBUF,
      I1 => SH1_OBUF,
      I2 => SH2_OBUF,
      I3 => SH0_OBUF,
      I4 => XLXI_1_XLXN_13,
      O => PS
    );
  XLXI_1_XLXI_5 : OR2
    port map (
      I0 => XLXI_1_XLXN_3,
      I1 => CLR_IBUF,
      O => XLXI_1_XLXN_2
    );
  XLXI_1_XLXI_4 : AND4b2
    port map (
      I0 => SH3_OBUF,
      I1 => SH0_OBUF,
      I2 => SH2_OBUF,
      I3 => SH1_OBUF,
      O => XLXI_1_XLXN_3
    );
  XLXI_1_XLXI_3 : AND4b2
    port map (
      I0 => SL2_OBUF,
      I1 => SL1_OBUF,
      I2 => SL3_OBUF,
      I3 => SL0_OBUF,
      O => XLXI_1_XLXN_13
    );
  XLXI_3_XLXI_13 : AND2
    port map (
      I0 => XLXI_3_XLXN_39,
      I1 => XLXI_3_XLXN_38,
      O => XLXI_3_XLXN_37
    );
  XLXI_3_XLXI_12 : AND4b3
    port map (
      I0 => HL3_OBUF,
      I1 => HL1_OBUF,
      I2 => HL0_OBUF,
      I3 => HL2_OBUF,
      O => XLXI_3_XLXN_39
    );
  XLXI_3_XLXI_11 : AND4b3
    port map (
      I0 => HH3_OBUF,
      I1 => HH2_OBUF,
      I2 => HH0_OBUF,
      I3 => HH1_OBUF,
      O => XLXI_3_XLXN_38
    );
  XLXI_3_XLXI_10 : OR2
    port map (
      I0 => XLXI_3_XLXN_37,
      I1 => CLR_IBUF,
      O => XLXI_3_CLR1
    );
  XLXI_3_XLXI_3 : AND4b2
    port map (
      I0 => HL2_OBUF,
      I1 => HL1_OBUF,
      I2 => HL0_OBUF,
      I3 => HL3_OBUF,
      O => XLXI_3_XLXN_31
    );
  XLXI_9_XLXI_5 : XOR2
    port map (
      I0 => HH0_OBUF,
      I1 => XLXI_9_HH0,
      O => XLXI_9_HHO0
    );
  XLXI_9_XLXI_6 : XOR2
    port map (
      I0 => HH1_OBUF,
      I1 => XLXI_9_HH1,
      O => XLXI_9_HHO1
    );
  XLXI_9_XLXI_7 : XOR2
    port map (
      I0 => HH2_OBUF,
      I1 => XLXI_9_HH2,
      O => XLXI_9_HHO2
    );
  XLXI_9_XLXI_8 : XOR2
    port map (
      I0 => HH3_OBUF,
      I1 => XLXI_9_HH3,
      O => XLXI_9_HHO3
    );
  XLXI_9_XLXI_9 : XOR2
    port map (
      I0 => HL0_OBUF,
      I1 => XLXI_9_HL0,
      O => XLXI_9_HLO0
    );
  XLXI_9_XLXI_10 : XOR2
    port map (
      I0 => HL1_OBUF,
      I1 => XLXI_9_HL1,
      O => XLXI_9_HLO1
    );
  XLXI_9_XLXI_11 : XOR2
    port map (
      I0 => HL2_OBUF,
      I1 => XLXI_9_HL2,
      O => XLXI_9_HLO2
    );
  XLXI_9_XLXI_12 : XOR2
    port map (
      I0 => HL3_OBUF,
      I1 => XLXI_9_HL3,
      O => XLXI_9_HLO3
    );
  XLXI_9_XLXI_13 : XOR2
    port map (
      I0 => MH1_OBUF,
      I1 => XLXI_9_MH1,
      O => XLXI_9_MHO1