代码搜索：Carry
找到约 8,060 项符合「Carry」的源代码
代码结果 8,060
www.eeworm.com/read/198623/7920948
s exp.s
.globl exp, _exp
/
ldfps = 170100^tst
stfps = 170200^tst
ldexp = 176400^movif
stexp = 175000^movfi
/
/ exp accepts its argument and returns its result
/ in fr0. The carry bit is set if the result ove
www.eeworm.com/read/157786/11662983
v srlc32e_macro.v
//
// Module: SRLC32E_MACRO
//
// Description: SelectShiftRegister-II macro
// 32 bit Shift Register with Carry and Clock Enable
// Use template "SRLC16E.v"
//
// Device: VIRTEX-II Family
www.eeworm.com/read/464789/1525089
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ALUComb is
port(
ALUCombResult : out vl_logic_vector(31 downto 0);
out_Carry : out vl_logic;
out_Zero
www.eeworm.com/read/216499/4893009
s exp.s
.globl exp, _exp
/
ldfps = 170100^tst
stfps = 170200^tst
ldexp = 176400^movif
stexp = 175000^movfi
/
/ exp accepts its argument and returns its result
/ in fr0. The carry bit is set if the result ove
www.eeworm.com/read/195341/5112417
s exp.s
.globl exp, _exp
/
ldfps = 170100^tst
stfps = 170200^tst
ldexp = 176400^movif
stexp = 175000^movfi
/
/ exp accepts its argument and returns its result
/ in fr0. The carry bit is set if the result ove
www.eeworm.com/read/287791/4018108
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ALUComb is
port(
ALUCombResult : out vl_logic_vector(31 downto 0);
out_Carry : out vl_logic;
out_Zero
www.eeworm.com/read/379467/2673632
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity ALUComb is
port(
ALUCombResult : out vl_logic_vector(31 downto 0);
out_Carry : out vl_logic;
out_Zero
www.eeworm.com/read/369339/2801567
s exp.s
.globl exp, _exp
/
ldfps = 170100^tst
stfps = 170200^tst
ldexp = 176400^movif
stexp = 175000^movfi
/
/ exp accepts its argument and returns its result
/ in fr0. The carry bit is set if the result ove
www.eeworm.com/read/287119/8720001
h aes.h
#ifndef __AES_H
#define __AES_H
// I retain copyright in this code but I encourage its free use provided
// that I don't carry any responsibility for the results. I am especially
// happy to se
www.eeworm.com/read/174989/9565776
vhd mul32c.vhd
-- mul32c.vhdl parallel multiply 32 bit x 32 bit to get 64 bit unsigned product
-- uses add32 component and fadd component, includes carry save
-- uses VHDL 'generate' to hav